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EP0149213A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Vector processor

Assignee: Hitachi Ltd
•
Filing: 1984-12-21
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Granted: —
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Expires: 2004-12-21
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Abstract

Abstract A vector processor for sequentially reading out elements of a plurality of vector operands (OP1, OP2, OP3) and sequentially storing the results of operations to the vector operands, comprising: operand counters (51a, 51b, 51c) for indicating the element numbers for every operand; address registers (21a, 21b, 21c) for every operand; a first comparator (108) for comparing each element of the vector; maximum number registers (52a, 52b, 52c) for storing the maximum numbers of elements of the respective operands; a second comparator (53) for comparing the operand counter of each operand with the content of the maximum number registers (52a to 52c) of each operand with respect to each operand; and a control circuit (107) for independently updating the operand counters (51a to 51c) and operand address registers (21a a to 21c) of each operand in response to all of or parts of the outputs of the first and second comparators (108 and 53)

Inventors

  • 👤 Shunichi Torii
  • 👤 Keiji Kojima
  • 👤 Masahiro Hashimoto

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-01 17:22
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30025; G06F15/00; G06F15/76; G06F15/80; G06F15/8053; G06F15/8076; G06F9/30021; G06F9/30036

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 111 words
A vector processor comprising: memory means (90) for storing vector operands (OP1, OP2, OP3); operating means (100) for performing operations on the basis of first and second vector operands (OPl and OP2) from said memory means (90) and outputting a third vector operand (OP3) obtained as the result of said operations to said memory means (90); first to third indication means (51a, 51b and 51c) for indicating element numbers of said first to third vector operands (OPl to OP3) which are being processed at present by said operating means (100); and control means (107) for respectively independently controlling the respective ones of said first to third instructing means (51a to 51c).
Claim 2
Dependent Claim 111 words
A vector processor comprising: memory means (90) for storing vector operands (OP1, OP2, OP3); operating means (100) for performing operations on the basis of first and second vector operands (OPl and OP2) from said memory means (90) and outputting a third vector operand (OP3) obtained as the result of said operations to said memory means (90); first to third indication means (51a, 51b and 51c) for indicating element numbers of said first to third vector operands (OPl to OP3) which are being processed at present by said operating means (100); and control means (107) for respectively independently controlling the respective ones of said first to third instructing means (51a to 51c).
Claim 3
Dependent Claim 104 words
A vector processor according to Claim 1, further comprising: first to third holding means (52a, 52b and 52c) for holding the respective maximum numbers of elements of said first to third vector operands (OPl to OP3); first to third comparing means (53, 106, 108) for respectively comparing numbers indicated by said first to third indication means (51a to 51c) with numbers held in said first to third holding means (52a to 52c); and said control means including means (107) for controlling said first to. third indication means (51a to 51c) in response to outputs of said first to third comparing means (53, 106, 108).
Claim 4
Dependent Claim 52 words
A vector processor according to claim 1, further comprising: fourth to sixth indication means for indicating readout addresses of said first to third vector operands (OP1 to OP3) which are to be read out from said memory means (90); and control means for respectively independently controlling said fourth to sixth indication means.

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