Patent EP0149048A1 successfully refreshed from Google Patents.
EP0149048A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method and apparatus for testing semiconductor devices
Assignee: International Business Machines Corp
•
Filing: 1984-11-14
•
Granted: —
•
Expires: 2004-11-14
Abstract
Abstract An array testing apparatus including a plurality of pin pattern generators (24) for individually generating serial bit sequences required at each pin (20) of a device (18) under test during the testing operation. The individual pin pattern generators (24) receive starting addresses from one or more programmable controllers (26) and each pin pattern generator (24) then performs a subroutine to repeat basic patterns or combinations of basic patterns as necessary. Both the pin pattern generators (24) and the programmable controllers (26) may include loop logic for obtaining the desired repetition sequences.
Inventors
- 👤 Yi-Hua E. Chang
- 👤 Algirdas J. Gruodis
- 👤 Hans P. Muhlfeld, Jr.
- 👤 Charles W. Rodriguez
- 👤 Mark L. Shulman
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 13:59
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/56; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31919; G01R31/31921; G01R31/3193; G01R31/31935; G11C29/04; G11C29/08; G11C29/12; G11C29/36; G01R31/31926
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
116 words
Method for testing semiconductor arrays having a plurality of terminal pins, by applying a sequence of input test vectors to said array terminal pins, monitoring the response data from said arrays, and comparing said response data to expected data of properly operating arrays, characterized in that each said test vector includes a plurality of bits each of which is applied to a respective one of said array terminal pins (20), each terminal pin (20) receiving a serial pattern of bits as its respective portion of said sequence of vectors, each of said patterns of bits for a respective one of said terminal pins (20) being generated separately by one of a plurality of pattern generators (24).
Claim 2
Dependent Claim
116 words
Method for testing semiconductor arrays having a plurality of terminal pins, by applying a sequence of input test vectors to said array terminal pins, monitoring the response data from said arrays, and comparing said response data to expected data of properly operating arrays, characterized in that each said test vector includes a plurality of bits each of which is applied to a respective one of said array terminal pins (20), each terminal pin (20) receiving a serial pattern of bits as its respective portion of said sequence of vectors, each of said patterns of bits for a respective one of said terminal pins (20) being generated separately by one of a plurality of pattern generators (24).
Claim 3
Dependent Claim
50 words
Method in accordance with claim 1, characterized in that at least one basic pattern of bits is stored in a pattern memory (64) out of which said basic pattern is read a predetermined number of times to obtain said serial pattern of bits, under the control of repeat control bits.
Claim 4
Dependent Claim
54 words
Method in accordance with claim 2, characterized in that said pattern memory (64) stores a plurality of basic patterns, and that said repeat control bits de- dermine the read-out of said basic patterns, combinations of basic patterns, and sequences of combinations of said basic patterns, in order to obtain said serial patterns of bits.
Claim 5
Dependent Claim
65 words
Method in accordance with claim 2, characterized in that an address to said pattern memory (64) is generated for reading out a pattern memory word stored at said address, said pattern memory word including at least one of said basic patterns as well as repeat control bits for controlling the combinations and repetitions of basic patterns to be read out of said pattern memory (64).
Claim 6
Dependent Claim
78 words
Method in accordance with claim 3, characterized in that the output signal of the pattern memory (64) is used for generating an output signal in N-bit parallel form representing said serial pattern of bits, said N-bit parallel output signal causing the said serial bit pattern to be applied to a respective one of said array terminal pins (20), wherein N is a number less than the number of bits in the output signal from said pattern memory (64).
Claim 7
Dependent Claim
85 words
Method in accordance with claim 5, characterized in that the response of said array terminal pins (20) is monitored by receiving response data from a portion of said plurality of terminal pins (20), and comparing said response data to expected data, each said pattern generator (24) providing, from a control latch (68) thereof, an output signal causing a driver/receiver circuit (72) to receive said response data, and an output circuit (70) to provide the expected data by reading them out of the pattern memory (64).
Claim 8
Dependent Claim
51 words
Method in accordance with claim 6, characterized in that said response data and said expected data are compared in a comparator (74) in accordance with mask data derived from a portion of the output from said pattern memory (64) under the control of the output signal from said control latch (68).
Claim 9
Dependent Claim
57 words
Method in accordance with claim 7, characterized in that an error load signal and an error flag signal are generated by said comparator (74) in case an error is detected between said response data and said expected data, the error load signal causing the error data to be transferred to and stored in an error memory (GO).
Claim 10
Dependent Claim
94 words
Method in accordance with claim 8, characterized in that said response data are received in N-bit parallel form during successive periods of time and compared to said expected data during each of said successive periods of time, at least two consecutive comparison signals being stored by said error memory (80), said error flag signal being provided for a duration corresponding to a plurality of successive error data signals, and that a count output is generated by a counter (82) indicating the particular portion of the error flag signal in which the error was detected.
Claim 11
Dependent Claim
67 words
Method in accordance with claim 2, characterized in that said basic pattern of bits is read out from said pattern memory (64) a predetermined number of times by performing a subroutine in which a predetermined sequence of addresses is provided to said pattern memory (64), each said subroutine commencing at a respective starting address, a sequence of said starting addresses being provided by a programmable controller (26).
Claim 12
Dependent Claim
137 words
Apparatus for executing the method in accordance with claim 1, characterized by a pattern generating means (Fig. 5) for generating a sequence of patterns of bits, said pattern generating means comprising a programmable controller (26) for generating a first sequence of starting addresses, and a plurality of pin pattern generators (24) each responsive to a particular one of said starting addresses for applying at least a portion of said pattern of bits to a respective one of said plurality of terminal pins (20), and that said pin pattern generators (24) comprise a memory (64) for storing at least one basic bit pattern and control data representing repetition information, and means (62, 70) for reading at least one basic bit pattern out of said memory (64) a predetermined number of times in accordance with said stored repetition information.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.