A video display control circuit

Claim 2

Apparatus for controlling the display of digital color video data stored in a video random access memory (1), characterized in that it comprises : main memory means (5) containing display data and being arranged to be addressed by said video data from said video access memory (1) fed into an address input of said main memory means (5): buffer memory means (13) having inputs arranged to receive display data and outputs connected to display data inputs of said main memory means (5); control means (11,3,24) operably connected to said main memory means (5) and said buffer memory means (13) for enabling transfer of said display data in said buffer memory means (13) to said main memory means (5) during a time when said data from said video random access memory (1) is not addressing said main memory means (5); and digital-to-analog convertor means (8,9,10) connected to outputs of said main memory means (5) for converting display data output therefrom to analog signals for display.

Claim 3

Apparatus according to claim 1, characterized in that said control means (11,3,24) includes timing control signal generator means (11) receiving as input signals a clock signal, a vertical sync signal, and a horizontal sync signal corresponding to said video display for producing a display data address signal fed to said main memory means (5) and to said buffer memory means (13), and for producing read/write timing control signals fed to said main memory means (5) and to said buffer memory means (13) being derived from said input signals fed to said timing control signal generator means (11).

Claim 4

Apparatus according to claim 2, characterized in that said control means further includes a first selector switch (3) for selectively connecting either said video data from said video random access memory (1) or said display data address signals from said timing control signal generator means (11) to said address input of said main memory means (5), and a second selector switch (24) for selectively connecting either said digital display address signals from said timing control signal generator means (11) or said display data to said buffer memory means (13).

Claim 5

Apparatus according to claim 3, characterized in that said digital-to-analog convertor means (8,9,10) includes three digital-to-analog convertors (8,9,10) each connected to receive a proportionate share of data output from said main memory means (5) and for respectively converting said data to corresponding analog signals.

Claim 6

Apparatus according to claim 1, characterized in that said data in said video random access memory (1) is arranged as pixels consisting of n bits and said data in said main memory means (5) comprises m bits per address, where m is greater than n.

Claim 7

Apparatus according to claim 5, characterized in that n = 4, m = 12 and said output of said main memory means (5) is arranged as three separate groups, each group having four bits of data.

Claim 8

Apparatus according to claim 6, characterized in that said digitial-to-analog convertor means (8,9,10) includes three digital-to-analog convertors (8,9,10) each connected to a respective group of said four-bits of data from said main memory means (5).

Claim 11

Apparatus according to claim 8, characterized in that said control circuit (11,3,24) includes a timing control signal generator (11) having inputs connected to a clock signal, a vertical synchronization signal, and a horizontal synchronization signal, corresponding to said video display, for producing display data address signals fed to said main memory means (5) and said buffer memory means (13) and for producing timing control signals fed to said main memory (5) and said buffer memory means (13).

Claim 12

A system according to claim 9, characterized in that said control circuit (11,3,24) includes a first selector switch (3) for selectively connecting either said data from said video random access memory (1) or said display data address signals from said timing control signal generator (11) to said address terminals of said main memory means (5), and a second selector switch (24) for selectively connecting either said display data address signal from said control signal generator (11) or said display data to said buffer memory means (13).

Claim 13

A system according to claim 10, characterized in that said digital-to-analog convertor means (8,9,10) includes three digital-to-analog convertors (8,9,10) each connected to receive a proportionate share of data output from said main memory means (5) and for respectively converting said data to corresponding analog signals.

Claim 14

A system according to claim 8, characterized in that said original video data in said video access memory (1) is arranged as pixels consisting of n bits and said display data in said main memory means comprises m bits per address, where m is greater than n.

Claim 15

A system according to claim 12, characterized in that n = 4, m = 12, and said output of said main memory means (5) is arranged as three separate groups, each group having four bits of data.

Claim 16

A system according to claim 13, characterized in that said digital-to-analog convertor means (8,9,10) includes three digital-to-analog convertors (8,9,10) each connected to a respective group of said four-bits of data from said main memory means (5).

Claim 17

A system according to claim 8, characterized in that said control means (11,3,24) includes a flip-flop circuit (15) connected to said timing signal control generator (11) for producing a signal indicating the end of an address sequence.

Claim 18

A video display control circuit for controlling the display of a video signal on a cathode ray tube, characterized in that it comprises : a video random access memory (1) arranged to store digital values of said video signal and producing outputs therefrom representing pixels of said video signals ; a main look-up table memory (5) having address inputs, data inputs, and data outputs; a buffer look-up table memory (13) having address inputs, data inputs connected to receive display data, and data outputs connected to said data inputs of said main look-up table (5); a timing control signal generator (11) receiving horizontal and vertical sync video signals and a video clock signal for producing therefrom sequential address signals and timing and control signals fed to said main look-up table memory (5) and said buffer look-up table memory (13); first selector switch means (3) having an output connected to said address inputs of said main look-up table memory (5) and for selectively connecting outputs from said video random access memory (1) or said sequential addresses from said timing control signal generator (11) to said address inputs of said main look-up table memory (5) in response to said control signal from said timing signal generator (11); second selector switch means (24) having an output connected to said address inputs of said buffer look-up table memory (13) for selectively connecting display data address information or said sequential addresses from said timing signal control generator (11) to said output in response to said control signal from said timing signal control generator (11); and digital-to-analog convertor means (8,9,10) connected to said outputs of said main memory means (5) for converting display data output therefrom to analog signals for display on said cathode ray tube.

Claim 19

A video display control circuit for controlling the display of a video signal on a cathode ray tube, characterized in that it comprises : a video random access memory (1) arranged to store digital values of said video signal and producing outputs therefrom representing pixels of said video signals ; a main look-up table memory (5) having address inputs, data inputs, and data outputs; a buffer look-up table memory (13) having address inputs, data inputs connected to receive display data, and data outputs connected to said data inputs of said main look-up table (5); a timing control signal generator (11) receiving horizontal and vertical sync video signals and a video clock signal for producing therefrom sequential address signals and timing and control signals fed to said main look-up table memory (5) and said buffer look-up table memory (13); first selector switch means (3) having an output connected to said address inputs of said main look-up table memory (5) and for selectively connecting outputs from said video random access memory (1) or said sequential addresses from said timing control signal generator (11) to said address inputs of said main look-up table memory (5) in response to said control signal from said timing signal generator (11); second selector switch means (24) having an output connected to said address inputs of said buffer look-up table memory (13) for selectively connecting display data address information or said sequential addresses from said timing signal control generator (11) to said output in response to said control signal from said timing signal control generator (11); and digital-to-analog convertor means (8,9,10) connected to said outputs of said main memory means (5) for converting display data output therefrom to analog signals for display on said cathode ray tube.