Programmable video display generator

Claim 2

A video display system having a microprocessor, memory, control section and interface section wherein the interface section comprises: clock circuitry for providing clocking signals for the video display system; memory timing circuitry receiving an input from the clock circuitry and providing memory control signals; control registers for receiving inputs from the microprocessor and the memory for providing a control input to the memory timing circuitry and to the clock circuitry; a microprocessor select circuitry receiving inputs from the microprocessor and the clock circuitry for providing an output indicating to which circuitry the microprocessor is sending commands; and a multiplexer for receiving addresses from the microprocessor and converting the addresses into row and column addresses; and wherein the control section comprises a data handler coupled to the microprocessor and the memory for latching and routing data within the video display system; a plurality of registers coupled to the data handler for temporarily storing data from the data handler; a decoder coupled to the plurality of registers for decoding; a character generator coupled to the decoder for storing character pattern information; a byte reducer coupled to the plurality of registers and receiving bytes of data and reducing the bytes to picture element size; logic circuitry coupled to receive inputs from the byte reducer, the decoder, and the character generator for implementing attributes to video to be displayed; a first shift register coupled to receive data from the logic circuitry for controllably shifting out data from any location within the first shift register to achieve scrolling of the video in one direction; object circuitry coupled to the data handler for receiving object data to generate a display for the object; a second shift register coupled to the object circuitry and to the plurality of registers for shifting data out; a priority circuit coupled for receiving data from the second shift register and the first shift register to determine priority of the data on a picture element by picture element basis; a color mapping RAM coupled for receiving data from the priority and the data handler and providing color data; a display address generator receiving inputs from the decoder and the microprocessor and providing memory addresses; and a memory map and controller coupled for receiving inputs from the microprocessor and the display address generator for decoding addresses.

Claim 3

The video display system of claim 1 wherein the interface section further includes a path encoder coupled between the control registers and the multiplexer to provide information on type of memory being used; and circuitry for providing information on type of microprocessor being used.

Claim 4

The video display system of claim 1 wherein the control section further comprises temporary storage coupled between the plurality of registers and the decoder; and circuitry for reporting collisions coupled between the second shift register and the memory map and controller.

Claim 5

The video display system of claim 1 wherein the decoder is a programmable logic array, and the byte reducer includes a latch and multiplexer.

Claim 6

A programmable video display generator for use in a video display system having a microprocessor, memory, and display unit, the programmable video display generator including an interface unit and a control unit wherein the interface unit comprises: first means for identifying type of microprocessor being used; second means for providing clocking signals for the video display unit; third means receiving an input from the second means and providing memory control signals; fourth means coupled to the microprocessor for temporarily storing control signals and providing an output to the third means; fifth means receiving inputs from the microprocessor and providing addressing signals to which circuit the microprocessor is communicating; sixth means receiving addresses from the microprocessor and temporarily storing the addresses; seventh means receiving inputs from the second and fourth means to provide an output indicative of type of random access memory being used; and eighth means receiving inputs from the sixth and seventh means and providing row and column addresses for the random access memory; and the control unit comprises: ninth means for receiving data and routing the data to its proper distination; tenth means for receiving data from the ninth means and temporarily storing the data; eleventh means receiving data from the tenth means and arranging the data to represent a character; twelfth means receiving data from the eleventh means and decoding the data; thirteenth means receiving data from the twelfth means and providing output data in picture element pattern; fourteenth means receiving inputs from the twelfth and thirteenth means for implementing attributes for displayed information; fifteenth means receiving data from the tenth means and reducing the data to picture element size and providing an output to the fourteenth means; sixteenth means receiving inputs from the fourteenth means for allowing selectively accessing the data to provide scrolling of the displayed information; seventeenth means coupled for receiving data from the ninth means for handling data in object format; eighteenth means coupled for receiving data from the tenth and seventeenth means and shifting out data in object format; nineteenth means receiving data from the sixteenth and eighteenth means for determining priority of the data to be displayed; twentieth means receiving data from the twelfth means and from the microprocessor for generating display addresses; twenty-first means receiving data from the ninth and nineteenth means for providing color information; and twenty-second means receiving data from the twenty-first means and generating video color signals.

Claim 7

A programmable video display generator for use in a video display system having a microprocessor, memory, and display unit, the programmable video display generator including an interface unit and a control unit wherein the interface unit comprises: first means for identifying type of microprocessor being used; second means for providing clocking signals for the video display unit; third means receiving an input from the second means and providing memory control signals; fourth means coupled to the microprocessor for temporarily storing control signals and providing an output to the third means; fifth means receiving inputs from the microprocessor and providing addressing signals to which circuit the microprocessor is communicating; sixth means receiving addresses from the microprocessor and temporarily storing the addresses; seventh means receiving inputs from the second and fourth means to provide an output indicative of type of random access memory being used; and eighth means receiving inputs from the sixth and seventh means and providing row and column addresses for the random access memory; and the control unit comprises: ninth means for receiving data and routing the data to its proper distination; tenth means for receiving data from the ninth means and temporarily storing the data; eleventh means receiving data from the tenth means and arranging the data to represent a character; twelfth means receiving data from the eleventh means and decoding the data; thirteenth means receiving data from the twelfth means and providing output data in picture element pattern; fourteenth means receiving inputs from the twelfth and thirteenth means for implementing attributes for displayed information; fifteenth means receiving data from the tenth means and reducing the data to picture element size and providing an output to the fourteenth means; sixteenth means receiving inputs from the fourteenth means for allowing selectively accessing the data to provide scrolling of the displayed information; seventeenth means coupled for receiving data from the ninth means for handling data in object format; eighteenth means coupled for receiving data from the tenth and seventeenth means and shifting out data in object format; nineteenth means receiving data from the sixteenth and eighteenth means for determining priority of the data to be displayed; twentieth means receiving data from the twelfth means and from the microprocessor for generating display addresses; twenty-first means receiving data from the ninth and nineteenth means for providing color information; and twenty-second means receiving data from the twenty-first means and generating video color signals.

Claim 8

The programmable video display generator of claim 5 wherein the control unit further comprises twenty-third means receiving data from the eighteenth means and determining whether a collision has occurred among the object data.

Claim 9

A video display system which uses a horizontal sync signal to synchronize horizontal scan lines comprising the following method: shutting off briefly PEL clock and memory timing clock at the end of the line; and restarting the PEL and memory timing clocks in a consistent phase relationship with respect to the horizontal sync so that each scan line commences with the same phase thereby eliminating the need to have an integer number of picture element clock cycles in a horizontal line.

Claim 10

A video display system which uses a horizontal sync signal to synchronize horizontal scan lines comprising the following method: shutting off briefly PEL clock and memory timing clock at the end of the line; and restarting the PEL and memory timing clocks in a consistent phase relationship with respect to the horizontal sync so that each scan line commences with the same phase thereby eliminating the need to have an integer number of picture element clock cycles in a horizontal line.