Patent US3710482A successfully refreshed from Google Patents.
Patent EP0147998A2 successfully refreshed from Google Patents.
EP0147998A2
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EP
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Semiconductor IC output circuitry
Assignee: Fujitsu Ltd
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Filing: 1984-12-19
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Granted: —
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Expires: 2004-12-19
Abstract
Abstract As the number of output circuits in a semiconductor IC (e.g. a LSI or VLSI circuit) increases the chance of many large output circuits operating at a same instant increases, with consequent increased possibility of a malfunction due to induced switching noise. In order to avoid or mitigate this problem, the switching speed of a driving buffer circuit (G1) which drives an output buffer circuit (G2) is controlled. By reducing the switching capacity of the driving circuit (G2), the switching speed of the total circuit (G1 plus G2) is affected but not seriously, whereas noise is decreased very much. The control of the switching capacity of the driving buffer circuit can be performed by master slice technology.
Inventors
- 👤 Shigeru C/O Fujitsu Limited Fujii
- 👤 Kouichi C/O Fujitsu Limited Yamashita
- 👤 Tomoaki C/O Fujitsu Limited Tanabe
- 👤 Yoshio C/O Fujitsu Limited Kuniyasu
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 17:39
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/003; H03K19/00346; H03K19/00361; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
59 words
Semiconductor integrated circuit having plural output circuits, each said output circuit comprising: output buffer circuit which provides output signal to outer load; and driving buffer circuit which provides said output buffer circuit with signals, wherein switching speed of said driving buffer circuit is controlled not to exceed the switching speed of said output buffer circuit by a predetermined ratio.
Claim 2
Dependent Claim
59 words
Semiconductor integrated circuit having plural output circuits, each said output circuit comprising: output buffer circuit which provides output signal to outer load; and driving buffer circuit which provides said output buffer circuit with signals, wherein switching speed of said driving buffer circuit is controlled not to exceed the switching speed of said output buffer circuit by a predetermined ratio.
Claim 3
Dependent Claim
63 words
Semiconductor integrated circuit according to the claim 1, wherein: said output circuit comprises plural standard gate circuits having a predetermined standard patterns; said driving buffer circuit is composed by combining such standard gate circuits; the switching speed of said driving buffer circuit is adjusted by selecting the size and/or adjusting the number of standard gate circuits combined to form the driving buffer circuit.
Claim 4
Dependent Claim
19 words
Semiconductor integrated circuit according to claim 1 or 2, wherein said output circuit is composed by complementary MIS FETs.
Claim 5
Dependent Claim
26 words
4 . Semiconductor integrated circuit according to claim 1 or 2, wherein said output buffer circuit and driving buffer circuit are composed by silicon complementary circuit.
Claim 6
Dependent Claim
33 words
Semiconductor integrated circuit according to any preceding claim, wherein said predetermined ratio of the switching speed of said driving buffer circuit to that of said output buffer circuit is no more than five.
Claim 7
Dependent Claim
33 words
Semiconductor integrated circuits according to claim 2, wherein said standard gate circuits further comprises different size of FETs, and said output buffer circuit and driving buffer circuit are composed from different size FETs.
Claim 8
Dependent Claim
32 words
7 . Semiconductor integrated circuit according to the claim 6, wherein number of FETs composing the driving buffer circuit is less than the number of the PETs composing the output buffer circuit.
Claim 9
Dependent Claim
117 words
A semiconductor integrated circuit having a plurality of output -buffer-ci-rcuits, said output buffer circuit comprising: a plurality of units in final stages of said output buffer circuit connected to an output terminal; a plurality of units of driving buffer circuits connected to said final stage for driving said final stage; and wiring means for connecting selected one of said final stages and selected one of said driving buffer circuits, wherein at least one of output buffer circuit being the one which utilized one or more of said units for driving buffer circuit and the number of units for driving buffer circuit being less than the number of units used in final stage of said output buffer circuit.
Claim 10
Dependent Claim
117 words
A semiconductor integrated circuit having a plurality of output -buffer-ci-rcuits, said output buffer circuit comprising: a plurality of units in final stages of said output buffer circuit connected to an output terminal; a plurality of units of driving buffer circuits connected to said final stage for driving said final stage; and wiring means for connecting selected one of said final stages and selected one of said driving buffer circuits, wherein at least one of output buffer circuit being the one which utilized one or more of said units for driving buffer circuit and the number of units for driving buffer circuit being less than the number of units used in final stage of said output buffer circuit.
Claim 11
Dependent Claim
121 words
In a semiconductor integrated circuit outputting an output signal of and internal circuit through an output buffer circuit at an output terminal pad, the improvement is that: output buffer circuits are provided to corresponding output terminal pad; and said output buffer circuit comprises a driving gate connected to said internal circuit and a final output buffer stage connected to said driving gate and outputting said signal to said output terminal pad, said driving gate comprising a plurality of transistors, each of transistors, having a predetermined gate width and gate length, said final output buffer stage comprising a plurality of transistors, each of transistors having a gate length and a gate width greater than said predetermined gate width of said driving gate.
Claim 12
Dependent Claim
121 words
In a semiconductor integrated circuit outputting an output signal of and internal circuit through an output buffer circuit at an output terminal pad, the improvement is that: output buffer circuits are provided to corresponding output terminal pad; and said output buffer circuit comprises a driving gate connected to said internal circuit and a final output buffer stage connected to said driving gate and outputting said signal to said output terminal pad, said driving gate comprising a plurality of transistors, each of transistors, having a predetermined gate width and gate length, said final output buffer stage comprising a plurality of transistors, each of transistors having a gate length and a gate width greater than said predetermined gate width of said driving gate.
Claim 13
Dependent Claim
49 words
The semiconductor integrated circuit of claim 9 , further comprising: a predetermined number of transistors in said final output buffer stage are connected in parallel; and the number of transistors used in said driving gate is less than said predetermined number of transistors in said final output buffer stage.
Claim 14
Dependent Claim
160 words
An LSI or a VLSI having thousands or tens of thousands of gates, having main logic circuitry and output circuitry, the number of output gates in the output circuitry,exceeding one hundred (or exceeding two hundred), the output circuitry having many output circuits each comprising an output buffer circuit, handling large output current (large in comparison to current handled in the main logic circuitry), and a . driving buffer circuit for driving switching operation of the output buffer circuit with respect to the large output current, wherein the driving buffer circuit is constructed to have a switching speed, for driving switching operation of the output buffer circuit with respect to the large output current, which is less in relation to switching speed of the output buffer circuit than would normally-be provided in such an LSI or VLSI, thereby to bring about a reduction in noise induced by switching operation of the output buffer circuit with respect to the large output current.
Claim 15
Dependent Claim
160 words
An LSI or a VLSI having thousands or tens of thousands of gates, having main logic circuitry and output circuitry, the number of output gates in the output circuitry,exceeding one hundred (or exceeding two hundred), the output circuitry having many output circuits each comprising an output buffer circuit, handling large output current (large in comparison to current handled in the main logic circuitry), and a . driving buffer circuit for driving switching operation of the output buffer circuit with respect to the large output current, wherein the driving buffer circuit is constructed to have a switching speed, for driving switching operation of the output buffer circuit with respect to the large output current, which is less in relation to switching speed of the output buffer circuit than would normally-be provided in such an LSI or VLSI, thereby to bring about a reduction in noise induced by switching operation of the output buffer circuit with respect to the large output current.
Claim 16
Dependent Claim
186 words
An LSI or a VLSI having thousands or tens of thousands of gates, having main logic circuitry and output circuitry, the number of output gates in the output circuitry exceeding one hundred (or exceeding two hundred), the output circuitry having many output circuits each comprising an output buffer circuit, handling large output current, and a driving buffer circuit for driving switching operation of the output buffer circuit with respect to the large output current, wherein the driving buffer circuit is constructed to have a switching speed, for driving switching operation of the output buffer circuit with respect to the large output current, which is less in relation to switching speed of the output buffer circuit than would normally be provided in such an LSI or VLSI, but which is sufficient to substantially maintain switching speed of the output circuit as a whole at the level which would normally be provided, and without reduction in the current handling capacity of the output buffer circuit, to provide a reduced level of noise induced by switching operation of the output buffer circuit with respect to the large output current.
Claim 17
Dependent Claim
186 words
An LSI or a VLSI having thousands or tens of thousands of gates, having main logic circuitry and output circuitry, the number of output gates in the output circuitry exceeding one hundred (or exceeding two hundred), the output circuitry having many output circuits each comprising an output buffer circuit, handling large output current, and a driving buffer circuit for driving switching operation of the output buffer circuit with respect to the large output current, wherein the driving buffer circuit is constructed to have a switching speed, for driving switching operation of the output buffer circuit with respect to the large output current, which is less in relation to switching speed of the output buffer circuit than would normally be provided in such an LSI or VLSI, but which is sufficient to substantially maintain switching speed of the output circuit as a whole at the level which would normally be provided, and without reduction in the current handling capacity of the output buffer circuit, to provide a reduced level of noise induced by switching operation of the output buffer circuit with respect to the large output current.
Claim 18
Dependent Claim
152 words
An LSI or a VLSI having thousands or tens of thousands of gates, having main logic circuitry and output circuitry, the number of output gates in the output circuitry exceeding one hundred (or exceeding two hundred), the output circuitry having many output circuits each comprising an output buffer circuit, handling large output current, and a driving buffer circuit for driving switching operation of the output buffer circuit with respect to the large output current, wherein the driving buffer circuit is constructed to have a switching speed, for driving switching operation of the output buffer circuit with respect to the large output current, by the provision and selection at least one switching element in the driving buffer circuit of lower operating speed than is achievable for such a switching element in such an LSI or VLSI, such as to reduce the level of noise induced by switching operation of the output buffer circuit.
Claim 19
Dependent Claim
152 words
An LSI or a VLSI having thousands or tens of thousands of gates, having main logic circuitry and output circuitry, the number of output gates in the output circuitry exceeding one hundred (or exceeding two hundred), the output circuitry having many output circuits each comprising an output buffer circuit, handling large output current, and a driving buffer circuit for driving switching operation of the output buffer circuit with respect to the large output current, wherein the driving buffer circuit is constructed to have a switching speed, for driving switching operation of the output buffer circuit with respect to the large output current, by the provision and selection at least one switching element in the driving buffer circuit of lower operating speed than is achievable for such a switching element in such an LSI or VLSI, such as to reduce the level of noise induced by switching operation of the output buffer circuit.
Claim 20
Dependent Claim
162 words
A LSI or a VLSI having main logic circuitry operable on the basis of relatively small switching currents and output circuitry operable on the basis of relatively large switching currents, the output circuitry including a plurality-of output circuits, each output circuit having an output buffer circuit in which relatively large switching current is handled, and a driving buffer circuit, arranged for driving switching operation of the output buffer circuit, wherein the driving buffer circuit is constructed to have a switching speed, for the driving of the switching operation of the output buffer circuit, which is selected to provide a level of noise, induced by switching operation of the output buffer circuit, significantly lower than would be provided if the driving buffer circuit were constructed to have a maximum achievable switching speed for such a circuit (or if the driving buffer circuit were constructed to have a switching speed as indicated by generally accepted teaching for the design of such LSI or VLSI).
Claim 21
Dependent Claim
162 words
A LSI or a VLSI having main logic circuitry operable on the basis of relatively small switching currents and output circuitry operable on the basis of relatively large switching currents, the output circuitry including a plurality-of output circuits, each output circuit having an output buffer circuit in which relatively large switching current is handled, and a driving buffer circuit, arranged for driving switching operation of the output buffer circuit, wherein the driving buffer circuit is constructed to have a switching speed, for the driving of the switching operation of the output buffer circuit, which is selected to provide a level of noise, induced by switching operation of the output buffer circuit, significantly lower than would be provided if the driving buffer circuit were constructed to have a maximum achievable switching speed for such a circuit (or if the driving buffer circuit were constructed to have a switching speed as indicated by generally accepted teaching for the design of such LSI or VLSI).
Claim 22
Dependent Claim
39 words
An LSI or VLSI as claimed in any one of claims 11 to 14 wherein the switching speed of the driving buffer circuit is no more than five times faster than the switching speed of the output buffer circuit.
Claim 23
Dependent Claim
33 words
An LSI or VLSI as claimed in claim 15 wherein the switching speed of the driving buffer circuit is at least twice as fast as the switching speed of the output buffer circuit.
Claim 24
Dependent Claim
60 words
A semiconductor integrated circuit as claimed in any preceding claim, wherein the switching speed of th output buffer circuit is in the range from a few nanoseconds (e.g. 7 or 8 nanoseconds) to 50 nanoseconds, and the switching speed of the driving buffer circuit is from two to five times faster than the switching speed of the output buffer circuit.
Claim 25
Dependent Claim
49 words
A semiconductor integrated circuit as claimed in any one of claims 1 to 16, wherein the switching speed of the driving buffer circuit is in the range 1.5 nanoseconds to 10 nanoseconds and is from two to five times faster than the switching speed of the output buffer circuit.
Claim 26
Dependent Claim
110 words
An LSI or a VLSI having at least two thousand gates and/or more than forty pins on its package, having an output circuit comprising an output buffer circuit which provides an output signal to an external load, and a driving buffer circuit which provides said output buffer circuit with signals, wherein the switching speed of the output buffer circuit is in the range from a few nanoseconds (e.g. 7 or 8 nanoseconds) to 50 nanoseconds, and the switching speed of the driving buffer circuit is in the range 1.5 nanoseconds to 10 nanoseconds; and is from two to five times faster than the switching speed of the output buffer circuit.
Claim 27
Dependent Claim
110 words
An LSI or a VLSI having at least two thousand gates and/or more than forty pins on its package, having an output circuit comprising an output buffer circuit which provides an output signal to an external load, and a driving buffer circuit which provides said output buffer circuit with signals, wherein the switching speed of the output buffer circuit is in the range from a few nanoseconds (e.g. 7 or 8 nanoseconds) to 50 nanoseconds, and the switching speed of the driving buffer circuit is in the range 1.5 nanoseconds to 10 nanoseconds; and is from two to five times faster than the switching speed of the output buffer circuit.
Claim 28
Dependent Claim
63 words
An LSI or VLSI as claimed in claim 19, having main logic circuitry with an operating current of the order of one microamp per FET, or less, and wherein the output current delivered by the output circuit is of the order of 3 to 10 milliamps DC per output buffer gate and/or of the order of 40 milliamps peak per output buffer gate.
References Cited (Backward Citations)
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