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EP0147836A2
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Precharge-type carry chained adder circuit
Assignee: Toshiba Corp
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Filing: 1984-12-21
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Granted: —
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Expires: 2004-12-21
Abstract
Abstract In a precharge-type carry chained adder circuit, stages as represented by adders and treated thereby are grouped into a plurality of blocks (CG) each consisting of a plurality of stages when the propagating functions of the stages of each block are active, a carry signal reproduced from the preceding block is transferred to the succeeding blocks through a bypass circuit.
Inventors
- 👤 Nobuyuki C/O Patent Division Ikumi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 15:48
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/506; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/386; G06F2207/3872
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
95 words
A precharge-type carry chained adder circuit having a plurality of precharge-type carry chained adders connected in a cascade fashion, characterized in that said cascade of precharge-type chained adders is divided into blocks (CG), and there are provided a plurality of AND gates (G) for generating logical products of the carry reproducing functions of each block (CG), and a plurality of transfer control elements (TG) each for jumping a carry signal over any block (CG) from the preceding block (CG) to the succeeding block (CG) when the logic gate (G) connected to the block is active.
Claim 2
Dependent Claim
95 words
A precharge-type carry chained adder circuit having a plurality of precharge-type carry chained adders connected in a cascade fashion, characterized in that said cascade of precharge-type chained adders is divided into blocks (CG), and there are provided a plurality of AND gates (G) for generating logical products of the carry reproducing functions of each block (CG), and a plurality of transfer control elements (TG) each for jumping a carry signal over any block (CG) from the preceding block (CG) to the succeeding block (CG) when the logic gate (G) connected to the block is active.
Claim 3
Dependent Claim
59 words
The adder circuit according to claim 1, characterized by further comprising logic gate means (G) for logically multiplying the logic products from the plurality of said blocks (CG) applied thereto, and bypass circuit means for jumping a carry signal over a plurality of said blocks (CG) in response to the output signal from each of said logic gates (G).
Claim 4
Dependent Claim
20 words
The adder circuit according to claim 2, characterized in that said bypass circuit means includes a plurality of bypass circuits.
Claim 5
Dependent Claim
17 words
The adder circuit according to claim 1, characterized in that said adder circuit is constructed with CMOSs.
Claim 6
Dependent Claim
18 words
The adder circuit according to claim 1, characterized in that said transfer control elements are transfer gates (TG).
References Cited (Backward Citations)
No citation records indexed.
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