Error recovery method and apparatus

Claim 2

An error recovery apparatus in a data processing system comprising: a peripheral unit for storing data in a plurality of data blocks, each of said data blocks having a unique address; a memory for storing a first channel command word (CCW) chain, said memory having storage areas for storing data transferred from said peripheral unit; a controller connected between said memory and said peripheral unit for reading said data blocks from said peripheral unit and transferring said data blocks to said memory to store said data blocks in said storage areas determined by said first CCW chain, said controller having detecting means to detect an uncorrectable error in the transfer of the second or subsequent data block of said plurality of data blocks, and; processing means connected to said controller for generating a new CCW chain when an error occurs in a second or subsequent data block of said plurality of data blocks.

Claim 3

An error recovery apparatus in a data processing system comprising: a peripheral unit for storing data in a plurality of data blocks, each of said data blocks having an address; a memory for storing a first channel command word (CCW) chain, said memory having storage areas' -for storing data transferred from said peripheral unit; a controller connected between said memory and said peripheral unit for reading said data blocks from said peripheral unit and transferring said data blocks to said memory to store said data blocks in said storage areas determined by said first CCW chain, said controller having detecting means to detect an uncorrectable error in the transfer of the second or subsequent data block of said plurality of data blocks; a first register connected to said controller for storing the total number of data units in all data blocks successfully transferred to said memory; a second register connected to said controller for storing the address of the data block currently being transferred from said peripheral units to said memory; and processing means connected to said controller for generating a new CCW chain when an error occurs in a second or subsequent data block of said plurality of data blocks, said new CCW chain generated by said processing means by considering the contents of said first register, the contents of said second register, and said first CCW chain. relocation mechanism of the disc unit and does not raise any problems when only one data record is processed during execution of the CCW chain containing a single command.

Claim 4

An error recovery apparatus in a data processing system comprising: a peripheral unit for storing data in a plurality of data blocks, each of said data blocks having an address; a memory for storing a first channel command word (CCW) chain, said memory having storage areas' -for storing data transferred from said peripheral unit; a controller connected between said memory and said peripheral unit for reading said data blocks from said peripheral unit and transferring said data blocks to said memory to store said data blocks in said storage areas determined by said first CCW chain, said controller having detecting means to detect an uncorrectable error in the transfer of the second or subsequent data block of said plurality of data blocks; a first register connected to said controller for storing the total number of data units in all data blocks successfully transferred to said memory; a second register connected to said controller for storing the address of the data block currently being transferred from said peripheral units to said memory; and processing means connected to said controller for generating a new CCW chain when an error occurs in a second or subsequent data block of said plurality of data blocks, said new CCW chain generated by said processing means by considering the contents of said first register, the contents of said second register, and said first CCW chain. relocation mechanism of the disc unit and does not raise any problems when only one data record is processed during execution of the CCW chain containing a single command.

Claim 5

If a plurality of data records is required for processing one command and, moreover, if any errors occur in any but the first record of a plurality of records (i.e. a second or subsequent record), command retry cannot be executed. This is because, although a command retry must reexecute the command from beginning, or it must reexecute the transfer of the required data records from the beginning, the disc controller cannot relocate the initial data record because it is not the data record processed immediately beforehand. When the command retry cannot be executed in the above case, the disc controller stops processing the command and informs the CPU of the error situation. The CPU usually generates a command to recover the error after receiving the information of the error from the disc controller. However, the disc controller repeats only the command retry under the command control from the CPU and nothing happens because of the limitation discussed above. No error recovery takes place.

Claim 6

If a plurality of data records is required for processing one command and, moreover, if any errors occur in any but the first record of a plurality of records (i.e. a second or subsequent record), command retry cannot be executed. This is because, although a command retry must reexecute the command from beginning, or it must reexecute the transfer of the required data records from the beginning, the disc controller cannot relocate the initial data record because it is not the data record processed immediately beforehand. When the command retry cannot be executed in the above case, the disc controller stops processing the command and informs the CPU of the error situation. The CPU usually generates a command to recover the error after receiving the information of the error from the disc controller. However, the disc controller repeats only the command retry under the command control from the CPU and nothing happens because of the limitation discussed above. No error recovery takes place.

Claim 7

Since the disc controller does not execute any recovery processing in this case, there is a strong probability that the same error will occur again in the same data record.

Claim 8

Since the disc controller does not execute any recovery processing in this case, there is a strong probability that the same error will occur again in the same data record.

Claim 9

As described above, when the data necessary for processing one command covers a plurality of data records, and when an input-output error occurs in the second or subsequent data block, a problem occurs in that recovery can not be provided because it is the second or subsequent data block that contains the error even if it is an input-output error that should be recovered by a command retry.

Claim 10

As described above, when the data necessary for processing one command covers a plurality of data records, and when an input-output error occurs in the second or subsequent data block, a problem occurs in that recovery can not be provided because it is the second or subsequent data block that contains the error even if it is an input-output error that should be recovered by a command retry.

Claim 11

SUMMARY OF THE INVENTION

Claim 12

SUMMARY OF THE INVENTION

Claim 13

One object of the present invention is to provide an error recovery apparatus which can recover an input-output error that should originally be recovered by a command retry even if the input-output error occurs in an input-output command which requires data from a plurality of data blocks or records for processing.

Claim 14

One object of the present invention is to provide an error recovery apparatus which can recover an input-output error that should originally be recovered by a command retry even if the input-output error occurs in an input-output command which requires data from a plurality of data blocks or records for processing.

Claim 15

If an uncorrectable error occurs in the first data block, the data in the first block can be processed by execution of the existing input-output command.

Claim 16

If an uncorrectable error occurs in the first data block, the data in the first block can be processed by execution of the existing input-output command.

Claim 17

According to the present invention, data blocks that have been processed normally do not need to be processed again if the input-output error ocurs in the second or subsequent data block, and command retry can be applied directly to the data block in error when the data block which proved to contain the input-output error is made the first record retrieved by a new CCW chain. When an input-output error occurs in a second or subsequent data block, a new input-output command is produced so that the data block containing the input-output error is designated as the first record of the processing. Accordingly, the data blocks or records following the data block containing the input-output error are processed by the new input-output command to complete the execution intended by the first CCW chain containing a single command.

Claim 18

According to the present invention, data blocks that have been processed normally do not need to be processed again if the input-output error ocurs in the second or subsequent data block, and command retry can be applied directly to the data block in error when the data block which proved to contain the input-output error is made the first record retrieved by a new CCW chain. When an input-output error occurs in a second or subsequent data block, a new input-output command is produced so that the data block containing the input-output error is designated as the first record of the processing. Accordingly, the data blocks or records following the data block containing the input-output error are processed by the new input-output command to complete the execution intended by the first CCW chain containing a single command.

Claim 19

BRIEF DESCRIPTION OF THE DRAWINGS

Claim 20

BRIEF DESCRIPTION OF THE DRAWINGS

Claim 21

FIGURE 1 shows roughly the construction of a computer system having disc units as one embodiment of the present invention;

Claim 22

FIGURE 1 shows roughly the construction of a computer system having disc units as one embodiment of the present invention;

Claim 23

FIGURE 2 the record format in a disc medium of a disc unit;

Claim 24

FIGURE 2 the record format in a disc medium of a disc unit;

Claim 25

FIGURE 3 shows a block diagram of a disc controller of the present invention; and

Claim 26

FIGURE 3 shows a block diagram of a disc controller of the present invention; and

Claim 27

FIGURE 4 shows the data configuration within a main memory.

Claim 28

FIGURE 4 shows the data configuration within a main memory.

Claim 29

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Claim 30

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Claim 31

Hereinafter, one preferred embodiment of the invention will be described in detail with reference to the accompanying drawings.

Claim 32

Hereinafter, one preferred embodiment of the invention will be described in detail with reference to the accompanying drawings.

Claim 33

Figure 1 illustrates the construction of a computer system as one embodiment of the present invention. The drawing shows a CPU 1, a main memory 2, a channel 3, a disc controller 4, and disc units 5. These units 1-4 are connected to each other by data buses 40 and control signal lines 41.

Claim 34

Figure 1 illustrates the construction of a computer system as one embodiment of the present invention. The drawing shows a CPU 1, a main memory 2, a channel 3, a disc controller 4, and disc units 5. These units 1-4 are connected to each other by data buses 40 and control signal lines 41.

Claim 35

Figure 2 illustrates part of one track of one disc medium in a disc unit. The figure illustrates the case in which there are n data.blocks (hereinafter called "records") lla, llb..., lln in one track of a disc medium. Each record usually has an index portion (ID) on which is recorded index information including an address for record identification and its length, and a data portion (DATA) of recorded data. The ID portions are usually used as addresses for accessing specific records. Reference numerals 12a, 12b...12n denote the ID portions of the records lla, llb...lln, respectively, and reference numerals 13a, 13b...13n denote the data portions of the records lla, llb...lln, respectively. Reference numerals 10A and 10B denote index markers.

Claim 36

Figure 2 illustrates part of one track of one disc medium in a disc unit. The figure illustrates the case in which there are n data.blocks (hereinafter called "records") lla, llb..., lln in one track of a disc medium. Each record usually has an index portion (ID) on which is recorded index information including an address for record identification and its length, and a data portion (DATA) of recorded data. The ID portions are usually used as addresses for accessing specific records. Reference numerals 12a, 12b...12n denote the ID portions of the records lla, llb...lln, respectively, and reference numerals 13a, 13b...13n denote the data portions of the records lla, llb...lln, respectively. Reference numerals 10A and 10B denote index markers.

Claim 37

Figure 3 illustrates the internal construction of the disc controller concerning the present invention. Reference numeral 40 denotes a data bus used for transferring data between the channel 3 and the disc units 5, and for transferring input-output control data between the channel 3 and the disc controller 4. Reference numeral 41 denotes a control signal line used for input and output between the channel 3 and the disk unit 5. Reference numerals 42 and 43 denote counters counting the number of data units in each record transferred between disc units 5 and channel 3 to main memory 2, and 45 and 46 denote registers retaining the ID portions of the records. Reference numerals 44 and 47 denote data buses used for transferring the contents of counter 43 and register 46 to the data bus 40. Reference numeral 48 denotes an internal control flag of the disc controller 4.

Claim 38

Figure 3 illustrates the internal construction of the disc controller concerning the present invention. Reference numeral 40 denotes a data bus used for transferring data between the channel 3 and the disc units 5, and for transferring input-output control data between the channel 3 and the disc controller 4. Reference numeral 41 denotes a control signal line used for input and output between the channel 3 and the disk unit 5. Reference numerals 42 and 43 denote counters counting the number of data units in each record transferred between disc units 5 and channel 3 to main memory 2, and 45 and 46 denote registers retaining the ID portions of the records. Reference numerals 44 and 47 denote data buses used for transferring the contents of counter 43 and register 46 to the data bus 40. Reference numeral 48 denotes an internal control flag of the disc controller 4.

Claim 39

The functions of the internal control flag 48, counters 42 and 43, and registers 45 and 46 of the disc controller 4 will now be described.

Claim 40

The functions of the internal control flag 48, counters 42 and 43, and registers 45 and 46 of the disc controller 4 will now be described.

Claim 41

The internal control flag 48 indicates whether the record that is now being processed is the first record or a second or subsequent record when a plurality of records are processed by one input-output command. It is reset automatically before the first record is processed, and is set at the beginning of the processing of the second record, after the first record has been processed successfully.

Claim 42

The internal control flag 48 indicates whether the record that is now being processed is the first record or a second or subsequent record when a plurality of records are processed by one input-output command. It is reset automatically before the first record is processed, and is set at the beginning of the processing of the second record, after the first record has been processed successfully.

Claim 43

The counter 42 counts the number of data units in the record currently exchanging input-output with the channel 3. It is reset by a control signal transferred through control signal line 41 before the start of the input-output of a certain record, and is incremented by the control signal whenever one data unit (usually 1 byte) is input or output. The counter 43 indicates the total number of data units that have been transferred successfully (with no error) when a plurality of records are being processed by one input-output command (CCW chain). It is reset when the transfer of the first record is started, and the count of the counter 42 is thereafter incremented by a count equal to the number of bits in the record transferred whenever the transfer of each record is completed without error.

Claim 44

The counter 42 counts the number of data units in the record currently exchanging input-output with the channel 3. It is reset by a control signal transferred through control signal line 41 before the start of the input-output of a certain record, and is incremented by the control signal whenever one data unit (usually 1 byte) is input or output. The counter 43 indicates the total number of data units that have been transferred successfully (with no error) when a plurality of records are being processed by one input-output command (CCW chain). It is reset when the transfer of the first record is started, and the count of the counter 42 is thereafter incremented by a count equal to the number of bits in the record transferred whenever the transfer of each record is completed without error.

Claim 45

Registers 45 and 46 are registers which store or retain the ID portions of the records transferred through the data bus 40. Register 45 retains the ID portion of the record that is currently being processed, and the storage of the ID portion is done simultaneously with the transfer of the content of the ID portion to the channel 3 when the ID portion is input to the main memory 2, and simultaneously with the transfer of the content of the ID portion to the disc unit 5 when the ID portion is output to the disc unit 5.

Claim 46

Registers 45 and 46 are registers which store or retain the ID portions of the records transferred through the data bus 40. Register 45 retains the ID portion of the record that is currently being processed, and the storage of the ID portion is done simultaneously with the transfer of the content of the ID portion to the channel 3 when the ID portion is input to the main memory 2, and simultaneously with the transfer of the content of the ID portion to the disc unit 5 when the ID portion is output to the disc unit 5.

Claim 47

Incidentally, the ID portion of a record is sometimes not necessary for processing a command, depending upon an input-output command, but even in such a case, the ID portion should always be read by the disc controller 4 and similarly retained in register 45 to carry out the present invention.

Claim 48

Incidentally, the ID portion of a record is sometimes not necessary for processing a command, depending upon an input-output command, but even in such a case, the ID portion should always be read by the disc controller 4 and similarly retained in register 45 to carry out the present invention.

Claim 49

The content of register 45 is transferred to register 46 when the input-output of the record ends normally. In other words, register 46 has the function of storing the ID portion of the record which was processed immediately before the record that is currently being processed.

Claim 50

The content of register 45 is transferred to register 46 when the input-output of the record ends normally. In other words, register 46 has the function of storing the ID portion of the record which was processed immediately before the record that is currently being processed.

Claim 51

Figure 4 illustrates roughly the data configuration of the main memory 2.

Claim 52

Figure 4 illustrates roughly the data configuration of the main memory 2.

Claim 53

A series of commands 50 (hereinafter called a "CCW chain") detailing the input-output processing shown in Figure 4 is stored in the main memory 2. Input regions 54, which include input regions 54a-54n, relating to the records lla through lln, are

Claim 54

A series of commands 50 (hereinafter called a "CCW chain") detailing the input-output processing shown in Figure 4 is stored in the main memory 2. Input regions 54, which include input regions 54a-54n, relating to the records lla through lln, are