Patent US1289082A successfully refreshed from Google Patents.
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EP0147295A2
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Data processing system including a plurality of multiprocessor systems
Assignee: Fujitsu Ltd
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Filing: 1984-12-17
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Granted: —
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Expires: 2004-12-17
Abstract
Abstract A data processor system includes a plurality of multiprocessor systems, and each multiprocessor system is connected through each memory control unit of each multiprocessor system. The multiprocessor system comprises a memory control unit, at least one central processing unit, at least one channel control unit, and at least one main memory unit. The central processing unit, channel control unit, and main memory unit are connected to the memory control unit via interface lines. The memory control unit (MCUO, MCU1) comprises at least two pipelines (PL1, PL11) and at least two access selecting circuits (S1, S2; S11, S12). One pipe-line (PL1) is used for access requests to the main memory unit belonging to the memory control unit, and the other pipe-line (PL11) is used for access requests to another main memory unit belonging to another memory control unit.
Inventors
- 👤 Hidehiko Nishida
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 20:43
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/1652; G06F13/1657
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
97 words
A data processor system including a plurality of multiprocessor systems, each multiprocessor system being connected through each memory control unit of each multiprocessor system, said multiprocessor system comprising, a memory control unit connected to the other multiprocessor system through interface lines for data transmission, at least one central processing unit connected to said memory control unit, and at least one main memory unit connected to said memory control unit, the central processing unit, channel control unit and main memory unit being connected to each other through said memory control unit by using interface lines for data transmission.
Claim 2
Dependent Claim
97 words
A data processor system including a plurality of multiprocessor systems, each multiprocessor system being connected through each memory control unit of each multiprocessor system, said multiprocessor system comprising, a memory control unit connected to the other multiprocessor system through interface lines for data transmission, at least one central processing unit connected to said memory control unit, and at least one main memory unit connected to said memory control unit, the central processing unit, channel control unit and main memory unit being connected to each other through said memory control unit by using interface lines for data transmission.
Claim 3
Dependent Claim
114 words
A'multiprocessor system as claimed in claim 1, wherein said memory control unit comprises a first pipe-line for controlling access request signals for the main memory unit connected to the memory control unit a second pipe-line for controlling access request signals for another main memory unit connected to another memory control unit, a first access selecting circuit for selecting an access request signal as to whether it is to access the main memory unit belonging to said first access selecting circuit or another main memory unit belonging to another memory control unit, and a second access selecting circuit for selecting an access request signal to another main memory unit belonging to another memory control unit.
Claim 4
Dependent Claim
25 words
A multiprocessor system as claimed in claim 2, wherein said second pipe-line is provided in the same number as the number of memory control units.
Claim 5
Dependent Claim
33 words
A multiprocessor system as claimed in claim 2, wherein said second access selecting circuit is provided in the same number as the number of memory-control units and belongs to each memory control unit.
Claim 6
Dependent Claim
40 words
A multiprocessor system as claimed in claim 2, wherein said first access selecting circuit is provided in the same number as the number of main memory units belonging to the memory control unit and belongs to each main memory unit.
Claim 7
Dependent Claim
57 words
A multiprocessor system as claimed in claim 2, wherein said memory control unit further comprises an address converter for converting a real address generated by said central processing unit to a physical address and is connected to said central processing unit and channel control unit at a previous stage of said first and second access selecting circuats.
Claim 8
Dependent Claim
31 words
A multiprocessor system as claimed in claim 2, wherein said memory control unit further comprises a discriminating circuit for discriminating access request signals for synchronous data transmission to another multiprocessor system.
Claim 9
Independent Claim
104 words
A method for processing data in a memory control unit provided in a multiprocessor system, said method comprising the steps of; selecting access request signals generated by a central processing unit as to whether they are for a main memory unit belonging to said central processing unit or for a main memory unit belonging to another memory control unit, transmitting -the selected access request signal when it is to be accessed another main memory unit belonging to another memory control unit, and processing both access request signals transmitted from said central processing unit and said another memory control unit based on the priority ranking.
Claim 10
Independent Claim
104 words
A method for processing data in a memory control unit provided in a multiprocessor system, said method comprising the steps of; selecting access request signals generated by a central processing unit as to whether they are for a main memory unit belonging to said central processing unit or for a main memory unit belonging to another memory control unit, transmitting -the selected access request signal when it is to be accessed another main memory unit belonging to another memory control unit, and processing both access request signals transmitted from said central processing unit and said another memory control unit based on the priority ranking.
Claim 11
Dependent Claim
19 words
A method as claimed in claim 7, wherein said memory control unit operates synchronously with another memory control unit.
References Cited (Backward Citations)
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