Process for forming isolating trenches in integrated circuit devices

Claim 1

Process for forming isolating trenches in integrated circuit devices in a semiconductor substrate by selectively etching through at least one trench-defining masking layer and at least one passivating layer disposed above the substrate, in order to reach down to the upper surface of said substrate, subsequent to an initial step of forming a pattern of openings through a conventional uppermost photoresist layer disposed above said trench-defining masking layer, characterized by the following steps: - plasma-depositing the trench-defining masking layer (84); - interposing between said trench-defining masking layer (84) and said uppermost photoresist layer (86) an organic underlayer (88) and a barrier layer (90) above said organic underlayer (88); - creating the conventional pattern of openings (92) through the uppermost photoresist layer (86), followed by selectively etching corresponding openings in said barrier layer (90); - selectively etching the organic underlayer (88) by using a selective etchant, whereby substantially perfectly vertical walls (94) are produced in the corresponding pattern of openings (92) in the organic underlayer (88); - extending said openings (92) by etching through said trench-defining masking layer (84) and said passivating layer (80, 82) down to said substrate (70); - removing said organic underlayer (88); - forming the isolation trenches (100) within the semiconductor substrate (70) by using a selective etchant to etch through said trench-defining masking layer (84) and into said substrate (70); and, - removing said trench-defining masking layer (84) by the use of an hydrofluoric acid (HF) solution such that the high etch ratio, which obtains between the trench-defining masking layer (84) and the passivating layer (80, 82) when such hydrofluoric acid (HF) solution is used, precludes significant etching of said passivating layer (80, 82).