Selective guest system purge control

Claim 3

A method according to claim 1 for handling address translations made by a guest system (guest) emulated on a multiprocessing system (MP) having a real main storage and a plurality of real CPUs, guest address translations being put into guest identified entries (guest entries) in a translation lookaside buffer (TLB) of any real CPU in the system while the CPU is in emulation state, the method further comprising: providing a unique CPU identifier (CPUID) for each real CPU in the MP, providing a state description control block (SD) in the real main storage for defining each uniprocessor (UP) guest, further characterized by: each SD containing a last CPU identifier field for identifying the last real CPU to use this SD, setting (35, 135) the respective CPUID into the last CPU identifier field in the SD for each guest dispatched upon any real CPU, comparing (33, 133) the content in the last CPU identifier field in the SD for a next guest being dispatched with the real CPU identifier (CPUID) for the real CPU upon which the guest is to be dispatched, invalidating (34, 134) all guest TLB entries for the said next guest in the CPU while the CPU is in emulation mode if the last CPU identifier field content compares unequal with the real CPU identifier or the content of the SDI field in the CPU compares unequal with the next SDI being provided, and not invalidating any guest TLB entry in the said CPU if the next SDI and the SDAR content compare equal and the last CPU identifier field and the real CPU identifier compare equal, so that the existing guest TLB entries in the CPU are allowed to be used by the guest for a guest program without retranslation.

Claim 4

A method as defined in Claim 2, further characterized by: providing a purge guest translation (PRGT) flag for each real CPU in the MP, setting on (43) the PRGT flag for all real CPUs in the system when executing a host program that invalidates a host page table entry in main storage, not immediately invalidating any existing guest TLB entries in the real CPU while the said host program is executing, testing (31) the PRGT flag for any real CPU on which a next guest is to be dispatched, invalidating (34) all existing guest TLB entries in the said real CPU if the said testing of the PRGT flag finds it on for this CPU, and resetting off (36) the PRGT field for this CPU, but not immediately invalidating any existing guest TLB entries in the said real CPU if the said testing of the PRGT flag finds it off for this CPU, so that the existing guest TLB entries can be used by the guest without retranslation.

Claim 5

A method as defined in Claim 2 or 3, further comprising: executing (40, 140) an invalidate page table entry (IPTE) instruction by the host program on a real CPU, invalidating a page table entry specified by the IPTE instruction (41, 141) and any existing host TLB entry in the translation lookaside buffer of this real CPU located by operand(s) of the IPTE instruction (42, 142), broadcasting (44, 144) by this real CPU to other real CPUs in the MP of an operand representation (45, 145) for the IPTE instruction for the host program, and completing (47, 48, 147, 148) processing for this IPTE instruction when all other real CPUs have indicated their response (77, 177).

Claim 6

A method as defined in Claim 4, further comprising: providing a guest MP control field (GMP) in real main storage for each virtual MP system (MP guest) which may execute in a real MP system, representing each virtual MP system with a plurality of state description control blocks (SDs) in real main storage, each SD representing a virtual CPU in the virtual MP system and a common virtual main storage for the virtual MP system, further providing a GMP address field (GMPA) in each SD, each SD of a virtual MP system containing an address to the same GMP, having an IPTE intercept flag field in each SD, the IPTE intercept flag being set off in the SD when a guest program is to execute a guest IPTE instruction instead of a host control program, testing (52) the state of the GMPA in the SD for a guest to determine if broadcasting to other CPUs is required, executing an IPTE instruction for a UP guest (53-55) on a real CPU for a virtual CPU if the test of the GMPA finds a zero content, but executing an IPTE instruction for a MP guest (58-68) on a real CPU for a virtual CPU if the test (52) of the GMPA finds a non-zero content.

Claim 7

A method as defined in Claim 5, further comprising: issuing (50) an invalidate page table entry (IPTE) instruction by a guest program dispatched for a UP guest being emulated on a real CPU of the MP, invalidating (53) a guest page table entry specified by the guest IPTE instruction being issued, also invalidating (54) any existing guest TLB entry for the current guest on this real CPU located by operand(s) of the issued IPTE instruction to complete the execution for the guest IPTE instruction, and not broadcasting any IPTE signals to any other real CPU, whereby the execution is completed (55) for a UP guest issuing an IPTE instruction in a MP system.

Claim 8

A method as defined in Claim 5 or 6, further comprising: issuing (50) an invalidate page table entry (IPTE) instruction by a guest program for a MP guest dispatched on a virtual CPU being emulated in the real MP, setting (59) to an on state a GMP addressed by the GMPA in the SD for the virtual CPU issuing the IPTE instruction, invalidating (61) a guest page table entry specified by the issued guest IPTE instruction, also invalidating (62) any guest TLB entry for the current guest located by operand(s) of the issued IPTE instruction in the real CPU on which the guest program is being executed for the MP guest, broadcasting (63) by the real CPU executing the guest program of an address for the issued IPTE instruction (64) to each other real CPU in the real MP which may be emulating a virtual CPU in the same virtual MP system as the broadcasting CPU, resetting (67) the GMP to an off state after (66) all real CPUs have responded (77) to the IPTE broadcasting, to complete (68) the processing of an IPTE instruction issued by a MP guest.

Claim 9

A method as defined in Claim 4, each other real CPU in the MP receiving the broadcasting operation, further comprising: invalidating (73, 173) in this real CPU any host TLB entry located by the broadcast IPTE operand representation for invalidating a host page frame, purging (75, 184) any guest TLB entry in this real CPU which addresses the host page being invalidated if (74) this CPU is in emulation state, but not purging any guest TLB entries in this CPU if this CPU is in host state, responding (77, 177) by this real CPU to the broadcasting CPU when this CPU completes processing for the broadcast IPTE instruction.

Claim 11

A method as defined in Claim 7, during which another real CPU in the real MP can be used by a host program which is simulating an instruction intercepted from a guest program on a virtual CPU of a MP guest in the real MP, the host program further comprising: making (200) a fetch or store request by the host program for an instruction being simulated, testing (201, 202) the state of a GMP accessed with a GMPA in a SD for the virtual CPU for which the instruction is being simulated by the host, setting (204) the GMP to an on state when the test finds the GMP is in an off state, the on state of the GMP indicating to other potential users of virtual storage of the MP guest that the MP guest's virtual storage is not available while the GMP is set to an on state, performing (205, 206) the fetch or store in the MP guest's virtual storage, setting (208) the GMP to off state when operations for the fetch or store request are completed, and continuing with the next host program operation.

Claim 12

A method as defined in Claim 10, further comprising: causing the invalidation of guest TLB entries for the current guest on all real CPUs in a real MP by setting a predetermined value for a CPUID in the SD for the same guest, such as by: assigning an all one's value as the predetermined value.

Claim 13

A method as defined in Claim 1, further comprising: assigning the address (SDA) of each SD in the system as the unique SD identifier (SDI) for each SD.