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EP0145497A2
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EP
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Semiconductor integrated circuit device
Assignee: Toshiba Corp
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Filing: 1984-12-13
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Granted: —
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Expires: 2004-12-13
Abstract
Abstract A master slice type LSI is constructed as a three port memory circuit in which respective cells exclusively utilized as memory circuits constituting respective memory regions can be accessed simultaneously. More particularly each cell exclusively used as a memory circuit is constituted by a llip-flop circuit including two inverters (31, 32) which are connected in parallel opposition, a single write data input line (39) and two read out data output lines (40, 41) which are connected to the flip-flop circuit through transfer gate circuits (33, 34, 35) respectively and at least three word lines (33, 34, 35) respectively and at least three word lines (36, 37, 38) along which independent word signals are transmitted. The three transfer gate circuit (33, 34, 35) are independently enabled and disenabled based on the word signals transmitted over the word lines (36, 37, 38).
Inventors
- 👤 Tomoji Takada
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 03:43
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
230 words
In a semiconductor integrated circuit device of the master slice type and comprising a semiconductor chip containing a plurality of basic cells which are integrated in a matrix, and a plurality of cells exclusively utilized as memory cells which constitute regions exclusively utilized as memory circuits, said integrated device manifesting desired logical performances based on a manner of wirings among respective cells, characterized in that the improvement wherein each one of said cells exclusively utilized as said memory circuits comprises first, second and third word lines (37,38,36) respectively transmitting three independent word signals; first and second read data output lines (40,41) a write data input line (39); first and second inverters (31,32) connected in parallel opposition for constituting a flip-flop circuit; a first transfer gate circuit enabled by a word signal transmitted over said first word line (37) for interconnecting said first read out data output line (40) and the output terminal of said first inverter (31); a second transfer gate circuit (35) enabled by a word signal transmitted over said second word line (36) for interconnecting said second read out data output line (41) and the output terminal of said first inverter 31; and a third transfer gate circuit (33) enabled by a word signal transmitted over said third word line (36) for interconnecting said write data input line (39) and the output terminal of said second inverter (32).
Claim 2
Dependent Claim
230 words
In a semiconductor integrated circuit device of the master slice type and comprising a semiconductor chip containing a plurality of basic cells which are integrated in a matrix, and a plurality of cells exclusively utilized as memory cells which constitute regions exclusively utilized as memory circuits, said integrated device manifesting desired logical performances based on a manner of wirings among respective cells, characterized in that the improvement wherein each one of said cells exclusively utilized as said memory circuits comprises first, second and third word lines (37,38,36) respectively transmitting three independent word signals; first and second read data output lines (40,41) a write data input line (39); first and second inverters (31,32) connected in parallel opposition for constituting a flip-flop circuit; a first transfer gate circuit enabled by a word signal transmitted over said first word line (37) for interconnecting said first read out data output line (40) and the output terminal of said first inverter (31); a second transfer gate circuit (35) enabled by a word signal transmitted over said second word line (36) for interconnecting said second read out data output line (41) and the output terminal of said first inverter 31; and a third transfer gate circuit (33) enabled by a word signal transmitted over said third word line (36) for interconnecting said write data input line (39) and the output terminal of said second inverter (32).
Claim 3
Dependent Claim
99 words
The semiconductor integrated circuit according to claim 1 wherein said first inverter (31) has a sufficiently large current drive power such that even when the output terminal of said first inverter is connected to either one or both of said first and second read out data liner (40,41) said flip-flop circuit will maintain its output logic level, whereas said second inverter (32) has a relatively small current drive power such that when the output terminal of said second inverter is connected to said write data input line (39), the output logic level of said flip-flop circuit would be inverted.
Claim 4
Dependent Claim
58 words
The integrated circuit device according to claim 1 wherein each of said cell exclusively used as memory circuits is connected to said first and second read out data output lines (41,41) and said device further comprises data latch means latching firstly read out data before arrival of said write data, while data are being written into said cell.
Claim 5
Dependent Claim
99 words
The semiconductor integrated circuit device according to claim 3 wherein said data latch means comprises a flip-flop circuit (54) which latches said read out data, a transfer gate circuit (56) contained in said flip-flop circuit (54) for enabling said flip-flop circuit based on a word signal transmitted over said third word line (36), and another transfer gate circuit (55) for interconnecting said first read out data output line (40) or said second read out data line (41) and said flip-flop circuit (54) based on an inverted logic signal of said word signal transmitted over said third word line (36).
References Cited (Backward Citations)
No citation records indexed.
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