Patent US4520820A successfully refreshed from Google Patents.
Patent EP0145357A2 successfully refreshed from Google Patents.
EP0145357A2
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Glitch lockout circuit for memory array
Assignee: AT&T Inc
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Filing: 1984-11-20
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Granted: —
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Expires: 2004-11-20
Abstract
Abstract @ The present invention relates to a glitch lockout circuit for a static random access memory (RAM) which prevents the writing or reading of incorrect data when a system clock is switched from a standard clock source to an alternate clock source. A dummy bit line (60) is added to the memory arrangement which is always precharged during a first clock phase (Φ1) and discharged during a second clock phase (Φ2). The state of the dummy bit line is latched with the first clock phase and is fed back to the clock generator to control the initiation of the second clock phase. Thus, if the dummy bit line stays low, the second clock phase will stay low and none of the RAM cells will be accessed.
Inventors
- 👤 Kevin David Kolwicz
- 👤 Gilbert Leroy Mowery, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 21:21
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4094; G11C11/41; G11C11/413; G11C11/417; G11C11/419; G11C7/00; G11C7/12; G11C7/14; G11C7/24
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
179 words
A memory arrangement comprising an array of memory cells arranged to occupy N rows and N columns; a plurality of N bit lines, each bit line associated with a separate one of the N rows of said array of memory cells: a clock source (M6) coupled to said plurality of N bit lines for precharging said plurality of N bit lines to a predetermined value during a first clock phase ($1) and accessing a selected memory cell during a second clock phase ($2): CHARACTERIZED BY a dummy bit line (60) responsive to the first clock phase from the clock source for precharging to the predetermined value and producing an output signal when said dummy bit line is completely precharged- and latching means (68) responsive to both the first clock phase and the dummy bit line output signal for producing an output signal when said first clock phase and said dummy bit line output signal coexist and applying said latching means output signal as an input to the clock source to initiate the second clock phase of the clock source.
Claim 2
Dependent Claim
179 words
A memory arrangement comprising an array of memory cells arranged to occupy N rows and N columns; a plurality of N bit lines, each bit line associated with a separate one of the N rows of said array of memory cells: a clock source (M6) coupled to said plurality of N bit lines for precharging said plurality of N bit lines to a predetermined value during a first clock phase ($1) and accessing a selected memory cell during a second clock phase ($2): CHARACTERIZED BY a dummy bit line (60) responsive to the first clock phase from the clock source for precharging to the predetermined value and producing an output signal when said dummy bit line is completely precharged- and latching means (68) responsive to both the first clock phase and the dummy bit line output signal for producing an output signal when said first clock phase and said dummy bit line output signal coexist and applying said latching means output signal as an input to the clock source to initiate the second clock phase of the clock source.
Claim 3
Dependent Claim
26 words
A memory arrangement formed in accordance with claim 1 wherein the dummy bit line precharges at a rate slower than the plurality of N bit lines.
Claim 4
Dependent Claim
35 words
. A memory arrangement formed in accordance with claim 1 wherein the dummy bit line comprises a plurality of transistor elements (62 - 62N) including like geometry as each memory cell of the memory array.
Claim 5
Dependent Claim
49 words
A memory arrangement formed in accordance with claim 1 wherein the latching means comprises a flip-flop circuit where the first clock phase is applied as a first input (CK) to the flip-flop and the dummy bit line output signal is applied as a second input (D) to the flip-flop.
References Cited (Backward Citations)
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