Electronic circuits and signal generator using them

Claim 2

Signal generator for generating a signal with pulses having sloping edges, characterized in that it includes a generator circuit (BSG) which is adapted to give said signal (BS+) in the time intervals between the pulses such an amplitude with respect to a second signal (BS-) that this amplitude may be detected by a detector circuit (CO) and in response thereto may be limited by a limiting circuit (S4) to a reference value.

Claim 3

Signal generator according to claim 1, characterized in that said signal generator (BSG) is coupled, on the one hand with said detector circuit which is constituted by a comparator circuit (CO) and on the other hand with a generator output (MNTC) which is coupled with said limiting circuit (S4) controlled by said comparator circuit, all in such a way that when both said signals are applied to said comparator circuit the pulse periods and the interpulse time intervals of said first signal (BS+) are detected as a consequence of which said comparator circuit (CO) controls said limiting circuit (S4) in such a manner that the latter limits said amplitude to said reference value in said interpulse time intervals.

Claim 4

Signal generator according to claim 2, characterized in that said generator circuit (BSG) is coupled via a first gating circuit (S3) with said generator output which is coupled to said reference value through a second gating circuit (S4) which constitutes said limiting circuit, said first (S3) and second (S4) gate circuits being controlled by complementary outputs (CR, CR) of said comparator circuit (CO) in such a manner that said first gating circuit (S3) allows the passage of said signals only during the pulse periods and that said second gating circuit (S4) limits the generator output (MNTC) to said reference value in the interpulse time intervals.

Claim 5

Signal generator according to claim 2, characterized in that it includes : a pulse source (PS, LSIC) which generates opposite first (PDM1) and second (PDM2) pulse waveforms, as well as a modulator circuit (CO) with a pair of first modulator inputs (BS+, BS-) to which said first (BS+) and second (BS-) signals are applied respectively, with a pair of second modulator inputs (PDM1, PDM2) to which said first (PDMl) and second (PDM2) pulse waveforms are applied, and with a modulator output which is coupled with said modulator output (BSO), said first modulator inputs (BS+, BS-) being coupled via a third (Sl) and a fourth (S4) gating circuit to said modulator output (BSO) respectively and said second modulator inputs (PDM1, PDM2) constituting control inputs of said third (Sl) and fourth (S2) gating circuits respectively, such that a pulse waveform (BSO) modulated by said first (BS+) and second (BS-) signals is generated at said modulator output (BSO).

Claim 6

Signal generator according to claim 4, characterized in that said opposite first (PDMl) and second (PDM2) pulse waveforms are pulse density modulated pulse waveforms and that said generator output (MNTC) is coupled with a filter device including a lowpass filter to transform said modulated pulse waveform into a modulated sine waveform.

Claim 7

Signal generator according to claim 5, characterized in that said filter device also includes a bandpass filter (BPF) to allow the passage of said sine waveform and to limit the amount of power in the lower frequency region thereof.

Claim 8

Signal generator according to claim 6, characterized in that said lower frequency region is the. speech region.

Claim 9

Signal generator according to claim 1, characterized in that said first (BS+) and second (BS-) are mutually inverse with respect to said reference value.

Claim 10

Signal generator according to claim 8, characterized in that said first (BS+) and second (BS-) signals are trapezoidal.

Claim 11

Signal generator according to claims 7 and 9, characterized in that said modulated sine waveform (BSO) is a metering signal for telecommunication purposes.

Claim 12

Signal generator according to claim 1, characterized in that said generator circuit include a pulse source (PS) generating a rectangular pulse waveform (PW) whose envelope alternately extends at different sides of said reference value, an operational amplifier (OAl) to the non-inverting input of which said rectangular pulse waveform (PW) is applied and whose output controls the operation of first (CSl) and second (CS2) current sources which are connected in series between the poles of a DC source (V+, V-), the junction point of said sources being coupled to the inverting input of said amplifier (OAl) and to one plate of a capacitor (C) whose other plate is connected to said reference value, said first signal (BS+) being generated at said junction point.

Claim 13

12 Signal generator according to claim 11, characterized in that said junction point is coupled to the non-inverting input of a unity gain second operational amplifier (OA2) and that the output of said second operational amplifier (OA2) is coupled with an inverting third operational amplifier (OA3) at the output of which said second signal (BS-) is generated.

Claim 14

Signal generator according to claims 3 and 4, characterized in that each of said gate circuits is constituted by a switch comprising two mutually coupled PMOS and NMOS transistors.

Claim 15

Comparator circuit with a first and a second input and with complementary first and second outputs, characterized in that said first (BS+) and second (BS-) inputs are coupled with first (Il) and second (I2) inputs of first (INVl) and second (INV2) inverters via first (NM8) and second (NM9) gating circuits, said inverters being coupled in a closed loop, a DC source being coupled via said inverters through a gating device (PM7, NM7) and said complementary outputs (CR, CR) being constituted by the inverter outputs (02, 01).

Claim 16

Comparator circuit with a first and a second input and with complementary first and second outputs, characterized in that said first (BS+) and second (BS-) inputs are coupled with first (Il) and second (I2) inputs of first (INVl) and second (INV2) inverters via first (NM8) and second (NM9) gating circuits, said inverters being coupled in a closed loop, a DC source being coupled via said inverters through a gating device (PM7, NM7) and said complementary outputs (CR, CR) being constituted by the inverter outputs (02, 01).

Claim 17

Comparator circuit according to claim 14, characterized in that each of said inverters (INVl, INV2) includes a PMOS transistor (PM5, PM6) and an NMOS transistor (NM5, NM6) the gate electrodes as well as the drain electrodes of which are commoned and constitute the inverter input (Il, I2) and output (Ol, 02) respectively, and the source electrodes of the PMOS transistors (PM5, PM6) and those of the NMOS transistors being coupled with respective poles of said DC source via third (PM7) and fourth gate circuits constituting said gating device, and said first and second gating circuits being conductive when said third and fourth gate circuits are not and vice-versa.

Claim 18

Modulator circuit with pairs of first and second inputs and with an output, characterized in that each of said first inputs (BS+, BS-) is coupled with said output (BSO) via first (Sl) and second (S2) gates and that said second inputs constitute respective control inputs of said first (Sl) and second (S2) gates.

Claim 19

Modulator circuit with pairs of first and second inputs and with an output, characterized in that each of said first inputs (BS+, BS-) is coupled with said output (BSO) via first (Sl) and second (S2) gates and that said second inputs constitute respective control inputs of said first (Sl) and second (S2) gates.