Semiconductor device structure including a dielectrically-isolated insulated-gate transistor

Claim 2

A semiconductor device structure comprising a substrate, a plurality of insulating tubs disposed on said substrate, and, disposed in each insulating tub, at least one respective semiconductor device, said insulating tubs dielectrically spacing the respective semiconductor device therein from the semiconductor devices in all other insulating tubs and also from the substrate, said semiconductor device structure further comprising: an insulated-gate transistor constituting one of said respective semiconductor devices and including, in successively adjoining relationship, a source region, a base region, a voltage-supporting region, and a minority-carrier injection region, each of said regions extending into said semiconductor device structure from a major, planar surface; said minority carrier injection region and said voltage-supporting region defining an interface therebetween, the entirety of which interface is oriented transverse to said major surface so as to enhance the current capacity of said insulated-gate transistor.

Claim 3

The semiconductor device structure of claim 1 wherein said voltage-supporting region and said base region define a second interface therebetween, said second interface being oriented in its entirety transverse to said major surface so as to permit high voltage operation of said insulated-gate transistor without the need for electric field rings therein.

Claim 4

The semiconductor device structure of claim 2 wherein said first-mentioned and said second interfaces are oriented in their entireties orthogonal to said major surface.

Claim 5

The semiconductor device structure of claim 1 wherein said insulating tub in which said insulated-gate transistor is disposed shares a common insulating portion with at least another of said plurality of insulating tubs.

Claim 6

The semiconductor device structure of claim 4 wherein, in said insulated-gate transistor, said source region, said base region, said voltage-supporting region and said minority-carrier injection region each comprise silicon semiconductor material.

Claim 7

The semiconductor device structure of claim 1 wherein said insulating tub in which said insulated-gate transistor is disposed is spaced from the remainder of said plurality of insulating tubs.

Claim 8

The semiconductor device structure of claim 6 wherein, in said insulated-gate-transistor, said source region, said base region, said voltage-supporting region and said minority-carrier injection region each comprise silicon semiconductor material.

Claim 9

A semiconductor device structure compris- i n g a substrate, a plurality of insulating tubs disposed on said substrate, and, disposed in each insulating tub, at least one respective semiconductor device, said insulating tubs dielectrically spacing the respective semiconductor device therein from the semiconductor devices in all other insulating tubs and also from the substrate, said semiconductor device structure further comprising: a bidirectional insulated-gate transistor constituting one of said respective semiconductor devices and including, in successively adjoining relationship, a first minority carrier injection region, a first base region, a voltage-supporting region, a second base region, and a second minority carrier injection region, each of said regions extending into said semiconductor device structure from a major, planar surface; said first minority carrier injection region and said first base region defining a first interface therebetween and said second minority carrier injection region and said second base region defining a second interface therebetween, said first and second interfaces being oriented in their entireties transverse to said major surface so as to enhance the current capacity of said bidirectional insulated-gate transistor.

Claim 10

A semiconductor device structure compris- i n g a substrate, a plurality of insulating tubs disposed on said substrate, and, disposed in each insulating tub, at least one respective semiconductor device, said insulating tubs dielectrically spacing the respective semiconductor device therein from the semiconductor devices in all other insulating tubs and also from the substrate, said semiconductor device structure further comprising: a bidirectional insulated-gate transistor constituting one of said respective semiconductor devices and including, in successively adjoining relationship, a first minority carrier injection region, a first base region, a voltage-supporting region, a second base region, and a second minority carrier injection region, each of said regions extending into said semiconductor device structure from a major, planar surface; said first minority carrier injection region and said first base region defining a first interface therebetween and said second minority carrier injection region and said second base region defining a second interface therebetween, said first and second interfaces being oriented in their entireties transverse to said major surface so as to enhance the current capacity of said bidirectional insulated-gate transistor.

Claim 11

The semiconductor device structure of claim 7 wherein said voltage-supporting region and said first base region define a third interface therebetween and said voltage-supporting region and said second base region define a fourth interface therebetween, said third and fourth interfaces being oriented in their entireties transverse to said major surface so as to permit high voltage operation of said bidirectional insulated-gate transistor without the need for electric field rings therein.

Claim 12

The semiconductor device structure of claim 9 wherein said first, second, third and fourth interfaces are oriented in their entireties orthogonal to said major surface.

Claim 13

The semiconductor device structure of claim 8 wherein said insulating tub in which said bidirectional insulated-gate transistor is disposed shares a common insulating portion with at least another of said plurality of insulating tubs.

Claim 14

The semiconductor device structure of claim 11 wherein, in said bidirectional insulated-gate transistor, said first and second minority carrier injection regions, said first and second base regions and said voltage-supporting region each comprise silicon semiconductor material.

Claim 15

The semiconductor device structure of claim 8 wherein said insulating tub in which said bidirectional insulated-gate transistor is disposed is spaced from the remainder of said plurality of insulating tubs.

Claim 16

The semiconductor device structure of claim 13 wherein, in said bidirectional insulated-gate transistor, said first and second minority carrier injection regions, said first and second base regions and said voltage-supporting region each comprise silicon semiconductor material.