Patent EP0144636A1 successfully refreshed from Google Patents.
EP0144636A1
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EP
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A programmable oscillator with power down feature and frequency adjustment
Assignee: International Business Machines Corp
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Filing: 1984-10-16
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Granted: —
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Expires: 2004-10-16
Abstract
Abstract A programmable oscillator (18) is provided for use on an integrated circuit chip. The oscillator (18) includes a plurality of inverted delay stages (80, 82, ...) connected in tandem between an input (INPUT) and an output node (Z). A single FET device (39) couples a common node (X) to a ground potential. Another FET device (31) controls the control node G. When a logic enabling signal is appropriately applied to the FET devices, the oscillator (18) is controlled so that internal nodes (G, H, ...) of the oscillator float high when it is off and no energy is dissipated. In addition, the ratio of delays between the delay stages (80, 82, ...) and the input stage (92) of the load (37) is such that the load (37) supplies the greater ratio of delays. This ensures that the oscillator's frequency of oscillation tracks the switching speed of the load (37).
Inventors
- 👤 Hayden Cranford, Jr.
- 👤 Stacy Jean Garvin
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 23:32
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/354; H03K3/027; H03K3/03; H03K3/0315; H03K3/64; H03K3/66; H03K3/70
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
154 words
An improved on-chip programmable oscillator (18) characterized in that it comprises: an input node (NIN); an output node (Z); a first means (80, 82, ...) coupled between the input and output node and operable to control the circuit delay and the frequency of oscillation; a second means (78) connected to the input node and operable for causing instability at the input node so as to initiate oscillation; a third means (92) responsive to an enabling signal and operable for supplying a control signal to the second means; a feedback path interconnecting the output node (Z line) to the first means and operable for ensuring the continuity of the oscillation; and a fourth means (31) operable to form a single conductive path between the first means and ground; said fourth means being responsive to an enabling signal and operable to disrupt the conductive path so that internal nodes are floated high to control power dissipation.
Claim 2
Dependent Claim
154 words
An improved on-chip programmable oscillator (18) characterized in that it comprises: an input node (NIN); an output node (Z); a first means (80, 82, ...) coupled between the input and output node and operable to control the circuit delay and the frequency of oscillation; a second means (78) connected to the input node and operable for causing instability at the input node so as to initiate oscillation; a third means (92) responsive to an enabling signal and operable for supplying a control signal to the second means; a feedback path interconnecting the output node (Z line) to the first means and operable for ensuring the continuity of the oscillation; and a fourth means (31) operable to form a single conductive path between the first means and ground; said fourth means being responsive to an enabling signal and operable to disrupt the conductive path so that internal nodes are floated high to control power dissipation.
Claim 3
Dependent Claim
30 words
The on-chip programmable oscillator of claim 1 further comprising a load means (37) coupled to the output node (Z) and operable to provide the largest proportion of the circuit delay.
Claim 4
Dependent Claim
35 words
The on-chip programmable oscillator of claim 1 wherein the third means further includes a pull-up electrical network (29') connected to the output node (Z) and operable to adjust the voltage level at said output node.
Claim 5
Dependent Claim
74 words
The on-chip programmable oscillator of claim 1 wherein the first means (80, 82, ...) includes a plurality of inverter stages connected in tandem with each stage being formed from a pair of FET devices (13, 13'; 15, 15'; ...) with at least one terminal of each device connected to a common node (G, H, ...), and an FET device (41, 41', ...) configured to operate as a capacitive load connected to the common node.
Claim 6
Dependent Claim
34 words
The on-chip programmable oscillator of claim 1 wherein the second means (78) includes an FET device (4) having a source electrode connected to the input node and a drain electrode connected to ground potential.
Claim 7
Dependent Claim
63 words
The on-chip programmable oscillator of claim 1 wherein the third means (92) includes an inverter stage comprising of a depletion mode FET device (33) poled to conductor current into a node; and a non-depletion mode FET device (39)connected to said node; said non-depletion mode FET device having an electrode connected to a ground potential and a gate electrode for receiving an enabling signal.
Claim 8
Dependent Claim
34 words
The on-chip programmable oscillator of claim 1 wherein the fourth means (31) includes an FEI device (31) having a gate electrode for receivii.j an enabling signal and another electrode connected to a ground potential.
References Cited (Backward Citations)
FR2199230A1
Cited
US4388536A
Cited
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