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Patent EP0142167A2 successfully refreshed from Google Patents.
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EP0142167A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Level shifting circuit

Assignee: NEC Corp
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Filing: 1984-11-13
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Granted: —
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Expires: 2004-11-13
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Abstract

Abstract A level shifting circuit for level shifting an input signal so as to correspond with the operating level of a logic circuit of the next stage. The level shifting circuit comprises a first CMOS inverting amplifier circuit (At) without provision of a feedback loop and a second CMOS inverting amplifier circuit (A 2 ) whose output is coupled to the input through a low impedance element (L1), either the input or the output of the second amplifier circuit (A 2 ) being connected to the input of the first amplifier circuit (A 1 . The second amplifier circuit (Aa) functions as an auto-bias circuit with respect to the first amplifier circuit (A 1 ). The level shifting circuitthus formed makes it possible to remarkably reduce power consumption and occupation area when configured as an integrated circuit.

Inventors

  • 👤 Masataka C/O Nec Corporation Mitami
  • 👤 Takashi C/O Nec Corporation Matsuura
  • 👤 Tatsuji Habuka
  • 👤 Tadakatsu Kimura

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-31 19:53
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 127 words
A level shifting circuit comprising a first CMOS inverting amplifier circuit (Al) to level shift an input signal which is inputted through an AC coupling capacitor (C) so as to correspond with the operating level of a logic circuit of the next stage, characterized in that there is provided a second CMOS inverting amplifier circuit (A2) whose input-output voltage characteristic is substantially idential to that of said first CMOS inverting amplifier circuit (Al), that said second CMOS inverting amplifier circuit (A2) have an . output and an input which are coupled to each other through low impedance means (Ll), and that either said input or output of said second CMOS inverting amplifier circuit (A2) is connected to said input of said first CMOS inverting amplifier circuit (Al).
Claim 2
Dependent Claim 127 words
A level shifting circuit comprising a first CMOS inverting amplifier circuit (Al) to level shift an input signal which is inputted through an AC coupling capacitor (C) so as to correspond with the operating level of a logic circuit of the next stage, characterized in that there is provided a second CMOS inverting amplifier circuit (A2) whose input-output voltage characteristic is substantially idential to that of said first CMOS inverting amplifier circuit (Al), that said second CMOS inverting amplifier circuit (A2) have an . output and an input which are coupled to each other through low impedance means (Ll), and that either said input or output of said second CMOS inverting amplifier circuit (A2) is connected to said input of said first CMOS inverting amplifier circuit (Al).
Claim 3
Dependent Claim 34 words
A level shifting circuit according to claim 1, wherein said low impedance means comprises an electrically conductive conductor through which said output and second input of said second CMOS inverting amplifier circuit are coupled.
Claim 4
Dependent Claim 26 words
A level shifting circuit according to claim 1 or 2, wherein said first and second CMOS inverting amplifier circuits are integrally formed into an integrated circuit.
Claim 5
Dependent Claim 37 words
A level shifting circuit according to any of claims 1 to 3 wherein each of said first and second CMOS inverting amplifier circuits comprises a pair of p-channel and n-channel MOS transistors complementarily connected to each other.

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