Microcode control system for digital data processing system

Claim 2

A control system for controlling a digital data processor which processes digital data in accordance with processing instructions in sequential processing cycles, each processing cycle being performed in one of a plurality of serially connected processing modules, said control system comprising: A. a like plurality of serially connected processing instruction receiving means, each receiving means being associated with one of said processing modules, said receiving means receiving the processing instruction and coupling it to the succeeding receiving means in synchronism with the transfer of said data through said processing modules, and B. a like plurality of decoding means each connected to one of said receiving means and one of said processing modules for decoding the processing instruction and generating control signals to control the connected processing module.

Claim 3

A control system as defined in claim 1 wherein said instruction receiving means comprise a series of latches connected seriatum, the processing instruction being shifted from an upstream latch to a downstream latch in each processing cycle.

Claim 4

A control system as defined in claim 1 wherein said decoding means are further connected to receive condition signals representative of processing conditions in the processor, the decoding means generating control signals in response to both the processing instruction and the condition signals.

Claim 5

A digital data processor which processes digital data in accordance with processing instructions in sequential processing cycles, comprising: A. a plurality of serially connected processing modules, each of which receives data from an upstream processing module, performs a processing operation on the data, and transmits the data to the downstream processing module; B. a like plurality of processing instruction storage means connected serially, each storage means being associated with one of said processing modules, said storage means receiving the processing instruction and coupling it to the succeeding receiving means in synchronism with the transfer of data through said processing modules, and C. a like plurality of decoding means each connected to one of said storage means and one of said processing modules for decoding the processing instruction and generating control signals to control the connected processing module.

Claim 6

A digital data processor which processes digital data in accordance with processing instructions in sequential processing cycles, comprising: A. a plurality of serially connected processing modules, each of which receives data from an upstream processing module, performs a processing operation on the data, and transmits the data to the downstream processing module; B. a like plurality of processing instruction storage means connected serially, each storage means being associated with one of said processing modules, said storage means receiving the processing instruction and coupling it to the succeeding receiving means in synchronism with the transfer of data through said processing modules, and C. a like plurality of decoding means each connected to one of said storage means and one of said processing modules for decoding the processing instruction and generating control signals to control the connected processing module.

Claim 7

A processor as defined in claim 4 wherein said instruction receiving means comprise a series of latches connected seriatum, the processing instruction being shifted from an upstream latch to a downstream latch in each processing cycle.

Claim 8

A processor as defined in claim 4 wherein said decoding means are further connected to receive condition signals representative of processing conditions in the processor, the decoding means generating control signals in response to both the processing instruction and the condition signals.

Claim 9

A processor as defined in claim 4 in which data are supplied from a plurality of data sources, one of said processing modules including means for selecting the data sources and for transmitting the data receiving from said data sources for processing in a downstream module.

Claim 10

A processor as defined in claim 4 wherein one of said processing modules includes means for performing an arithmetic operation on the data received from an upstream processing module.

Claim 11

A processor as defined in claim 4 wherein one of said processing modules includes means for storing indication means for indicating selected results of processing of the data received from an upstream module.

Claim 12

A processor as defined in claim 4 wherein each of said processing modules includes a processed storage means for storing the processed data transmitted therefrom, said processed data storage means storing the processed data in synchronism with the transfer of the processing instruction which controls the processing of the associated data between the processed data storage means.

Claim 13

A digital data processor for executing instructions comprising an operation code identifying an operation to be performed on operands from selected ones of a plurality of operand source means, the processor executing each instruction in accordance with a series of microinstructions from a microcode control store, the processor comprising: A. data path means including: (i) an operand selection stage connected to the operand source for selecting and storing operands during a processing cycle, (ii) an operand processor stage connected to the operand selection stage for processing the operands and storing the processed operands during a processing cycle; and B. microcode control means connected to said operand selection stage and said operand processor stage for enabling said respective stages to perform predetermined operations in execution of the microinstruction during a plurality of successive processing cycles, including: (i) microcode selection and transmitting means for receiving the operation code of the instruction, for identifying a series of microinstructions in response thereto, and for iteratively transmitting a microinstruction from the identified series, (ii) a plurality of microcode storage means connected serially for iteratively receiving the microinstructions from said microcode storage means or an upstream microinstruction storage means and for transferring the microinstruction to the next downstream storage means at the end of each cycle, each of said microcode storage means being associated with one of said processing stages, and (iii) a like plurality of decoding means each connected to one of said receiving means and one of said stages in said processing means for decoding the microinstruction and generating control signals to control the operations of the connected stage.

Claim 14

A digital data processor for executing instructions comprising an operation code identifying an operation to be performed on operands from selected ones of a plurality of operand source means, the processor executing each instruction in accordance with a series of microinstructions from a microcode control store, the processor comprising: A. data path means including: (i) an operand selection stage connected to the operand source for selecting and storing operands during a processing cycle, (ii) an operand processor stage connected to the operand selection stage for processing the operands and storing the processed operands during a processing cycle; and B. microcode control means connected to said operand selection stage and said operand processor stage for enabling said respective stages to perform predetermined operations in execution of the microinstruction during a plurality of successive processing cycles, including: (i) microcode selection and transmitting means for receiving the operation code of the instruction, for identifying a series of microinstructions in response thereto, and for iteratively transmitting a microinstruction from the identified series, (ii) a plurality of microcode storage means connected serially for iteratively receiving the microinstructions from said microcode storage means or an upstream microinstruction storage means and for transferring the microinstruction to the next downstream storage means at the end of each cycle, each of said microcode storage means being associated with one of said processing stages, and (iii) a like plurality of decoding means each connected to one of said receiving means and one of said stages in said processing means for decoding the microinstruction and generating control signals to control the operations of the connected stage.

Claim 15

A processor as defined in claim 11 in which at least one of said decoding means further receives a condition signal from said processor indicating the occurrence of selected conditions in said processor, said decoding means using said condition signal with said microinstruction to control the connected stage.

Claim 16

A processor as defined in claim 11 wherein said microinstruction storage means comprise a series of latches connected seriatum, the microinstruction being shifted from an upstream latch to a downstream latch in each processing cycle.

Claim 17

A processor system as defined in claim 11 wherein said decoding means are further connected to receive condition signals representative of processing conditions in the processor, the decoding means generating control signals in response to both the processing instruction and the condition signals.

Claim 18

A processor as defined in claim 11 wherein said operand processor stage includes means for performing an arithmetic operation on the data received from an upstream processing module.

Claim 19

A processor as defined in claim 11 wherein said operand processor stage includes means for storing indication means for indicating selected results of processing of the operand received from said operand selection stage.

Claim 20

A processor as defined in claim 11 wherein each of said operand selection stage and operand processor stage includes a processed operand storage means for storing the processed operand transmitted therefrom, said storage means operating in synchronism with the transfer of the microinstruction which controls the processing by the respective stage between the microinstruction storage means.

Claim 21

An exponent processor for processing exponent portions of operand words in a floating point processor in a digital data processing system, the exponent operands of the operand words being-provided from a plurality of operand sources, and being processed in connection with an instruction, the instruction identifying a series of microinstructions which define the procedure for processing the operand, the exponent processor comprising,: A. a data path comprising: (i) an exponent operand selection stage for selecting the sources of the operands from among the operand sources and for storing the exponent operands from the selected sources during a processing cycle, and (ii) an exponent processing stage connected to said exponent operand selection stage for processing the exponent operands and storing the processed exponent operands during a processing cycle, and B. microcode control means connected to said exponent operand selection stage and said exponent operand processor stage for enabling said respective stages to perform predetermined operations in execution of the microinstruction during a plurality of successive processing cycles, including: (i) microcode selection and transmitting means for receiving the operation code of the instruction, for identifying a series of microinstructions in response thereto, and for iteratively transmitting a microinstruction from the identified series, (ii) a plurality of microinstruction storage means connected serially for iteratively receiving the microinstructions from said microinstruction transmitting means or an upstream microinstruction storage means and for transferring the microinstruction to the next downstream storage means at the end of each cycle, each of said microcode storage means being associated with one of said exponent operand selection stage or said exponent processing stage, and (iii) a like plurality of decoding means each connected to one of said microinstruction storage means and one of said stages in said processing means for decoding the microinstruction and generating control signals to control the operations of the connected stage.

Claim 22

An exponent processor for processing exponent portions of operand words in a floating point processor in a digital data processing system, the exponent operands of the operand words being-provided from a plurality of operand sources, and being processed in connection with an instruction, the instruction identifying a series of microinstructions which define the procedure for processing the operand, the exponent processor comprising,: A. a data path comprising: (i) an exponent operand selection stage for selecting the sources of the operands from among the operand sources and for storing the exponent operands from the selected sources during a processing cycle, and (ii) an exponent processing stage connected to said exponent operand selection stage for processing the exponent operands and storing the processed exponent operands during a processing cycle, and B. microcode control means connected to said exponent operand selection stage and said exponent operand processor stage for enabling said respective stages to perform predetermined operations in execution of the microinstruction during a plurality of successive processing cycles, including: (i) microcode selection and transmitting means for receiving the operation code of the instruction, for identifying a series of microinstructions in response thereto, and for iteratively transmitting a microinstruction from the identified series, (ii) a plurality of microinstruction storage means connected serially for iteratively receiving the microinstructions from said microinstruction transmitting means or an upstream microinstruction storage means and for transferring the microinstruction to the next downstream storage means at the end of each cycle, each of said microcode storage means being associated with one of said exponent operand selection stage or said exponent processing stage, and (iii) a like plurality of decoding means each connected to one of said microinstruction storage means and one of said stages in said processing means for decoding the microinstruction and generating control signals to control the operations of the connected stage.

Claim 23

An exponent processor as defined in claim 18 in which said operand exponent selection stage includes a multiplexer connected to a plurality of exponent operand sources and a plurality of exponent operand storage means, each of which receives an exponent operand, said multiplexer coupling an exponent operand from one of a plurality of exponent operand sources to one of the exponent operand latches in response to a control signal from the associated decoding means.

Claim 24

An exponent processor as defined in claim 19 in which the decoding means associated with said exponent selection stage further includes means for receiving condition signals from at least one of the exponent operand sources which indicates the presence of an exponent operand therein, said decoding means including means for using the condition signals in connection with selecting the source of the exponent operands.

Claim 25

An exponent processor as defined in claim 19 in which said exponent processing stage includes an arithmetic and logic unit connected to said exponent operand storage means for performing arithmetic operations on the stored exponent operand in response to control signals from the associated decoding means.

Claim 26

An exponent processor as defined in claim 21 in which all of said said exponent operand storage means include sign storage means for storing a sign signal, said exponent operand processing means including sign processing means for generating a processed sign signal in response to control signals from the associated decoding means, said exponent operand processing means further including means for storing the output of said sign processing means.

Claim 27

An exponent processor as defined in claim 22 in which said exponent operand processing means includes exception processing means for generating condition signals in response to the presence of selected conditions during processing of an exponent operand, said exception processing means including means for storing the condition signals contemporaneously with the storage of processed exponent operands in said exponent processing stage.