Method for the operation of a multiprocessor controller, especially for the central control unit of a telephone switching system

Claim 1

A method for operating a multi-processor controller, particularly for the central control unit of a telephone switching system, wherein - at least some of the processors (BP, CP, IOC, IOP) have, via first switches (S) and, as a result, via each half (B:CMYO, B:CMY1) of a central bus system (B:CMY) doubled in itself, and second switches (SW connected) thereto, optional access - to each half of a main memory (CMY) doubled in itself, or, respectively, - to each half (for example MB3a and/or MB3b) of one or more memory banks (MB) doubled in themselves of the main memory (CMY) containing a plurality of such memory banks (MBO...MB3), characterised in that, in order to split off redundant parts of the controller during a special operating time and connect these parts to an independent separate special computer without interfering with the normal operation of the remaining controller, - individual redundant ones of these processors (for example CP9 and/or IOC1), together with one half (for example B:CMY1) of the bus system (B:CMY) and together with a part of the main memory (CMY) or with one or more halves of the memory banks (MB) of the main memory (CMY) are connected together to form an independent special computer for a special program, for example for preparing a new modification of the normal operating program of the controller, - Whereas in the remaining parts of the controller, that is to say in the remaining computer (BP, CP without CP9, IOCO with its IOP, B:CMYO, remainder of CMY) the previous normal operating program still runs, for example for switching-related functions, in order to terminate or interrupt the special program of the special computer later, at the latest when the remaining computer is overloaded, particularly in the case of a failure of an essential processor of the remaining computer - the components of the special computer, at least an essential part of its processors and/or at least its bus system half (B:CMY1) are again connected to the remaining computer in such a manner that thereafter, in any case essentially only the normal operating program or a modification thereof, newly entered during the special operating time, is now running.