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EP0140698A2
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Fault-tolerant memory array
Assignee: Atmel Corp
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Filing: 1984-10-29
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Granted: —
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Expires: 2004-10-29
Abstract
Abstract An array of memory cells (10-16) is organized as bytes of at least one bit in lenght, these memory cells being configured to conduct substantial current while in one of two states and not conduct substantial current while in the other of said two states and the arrangement being such that memory cells which fail when in operation do not conduct substantial current. The array is rendered fault-tolerant by the use of an address means (26) which simultaneously selects at least two of said bytes of memory cells and a sensing means which is connected to corresponding ones of the memory cells in the selected bytes of memory cells so as to the presence or absence of current flow in the corresponding ones of said memory cells.
Inventors
- 👤 George Perlegos
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 10:40
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/18; G06F11/187
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
117 words
A fault-tolerant memory array comprising an array of memory cells (10-16) organized as bytes of at least one bit in length, said memory cells being configured to conduct substantial current while in one of two states and not conduct substantial current while in the other of said two states and wherein memory cells which fail when in operation do not conduct substantial current, characterised by address means (26) for simultaneously selecting at least two of said bytes of memory cells and sensing means (38-44) connected to corresponding ones of said memory cells (10-16) in said selected bytes of memory cells for sensing the presence or absence of current flow in said corresponding ones of said memory cells.
Claim 2
Dependent Claim
117 words
A fault-tolerant memory array comprising an array of memory cells (10-16) organized as bytes of at least one bit in length, said memory cells being configured to conduct substantial current while in one of two states and not conduct substantial current while in the other of said two states and wherein memory cells which fail when in operation do not conduct substantial current, characterised by address means (26) for simultaneously selecting at least two of said bytes of memory cells and sensing means (38-44) connected to corresponding ones of said memory cells (10-16) in said selected bytes of memory cells for sensing the presence or absence of current flow in said corresponding ones of said memory cells.
Claim 3
Dependent Claim
87 words
A fault-tolerant memory array as claimed in claim 1 wherein said memory cells are arranged in a plurailty of rows and said address means receive address input signals indicative of a row of memory cells to be selected by said address means, said address means including a plurality of row lines respectively connected to said plurality of rows of memory cells such that at least two of said rows of memory cells are simultaneously activated for each of said addresing input signals received by said address means.
Claim 4
Dependent Claim
83 words
A fault-tolerant memory array as claimed in claim 2, wherein each of the address input signals comprises a series of address inputs and said address means includes a decoder means which generates complementary signals for each of said series of address inputs, said address means further including means for grounding the complementary signals associated with a pre-determined one of said series of address inputs in order to permit said address means to activate simultaneously at least two of said rows of memory cells.
Claim 5
Dependent Claim
85 words
A fault-tolerant memory array as claimed in claim 1, wherein said memory cells are arranged in a plurality of columns and said address means receives address input signals indicative of a column of memory cells to be selected by said memory means, said address means including a plurality of read lines respectively connected to said plurality of columns of memory cells such that at least two of said read lines are simultaneously selected for each of said address input signals received by said address means.
Claim 6
Dependent Claim
62 words
A fault-tolerant memory array as claimed in claim 4, wherein said sensing means includes a plurality of amplifiers respectively associated with said address input signals and a plurality of logic means of connecting all of the read lines, simultaneously selected in response to the receipt of a pre-determined address input signal, to the amplifier associated with the said pre-determined address input signals.
Claim 7
Dependent Claim
66 words
A fault-tolerant memory array as claimed in claim 1, wherein said sensing means includes at least one amplifier means for changing state depending upon the presence or absence of current flow in said corresponding ones of said memory cells, said amplifier means having a threshold for changing state which is adjusted beyond the level of current flow sensed from a failed one of said memory cells.
Claim 8
Dependent Claim
40 words
A fault-tolerant memory array as claimed in claim 1, wherein said memory cells characteristically exhibit a threshold voltage which is adjusted such that said sensing means senses the absence of current flow only when a memory cell has been programmed.
References Cited (Backward Citations)
No citation records indexed.
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