Digital phase lock loop circuit

Claim 2

A digital phase lock loop circuit comprising: a reference clock pulse generator whose clock frequency is selected to be higher than the recurrence rate of raw data pulses received from an external device; a pulse shaper for subjecting each of said data pulses to waveform-shaping to obtain waveform-shaped pulses having a pulse width approximately equal to one clock period of said reference clock pulse; means for comparing said waveform-shaped data pulses to a delayed reference clock pulse and for producing a phase control pulse on the basis of the relative positions of said delayed reference clock pulse and each of said waveform-shaped data pulses; and means for generating said delayed reference clock pulse in response to said phase control pulse.

Claim 3

A digital phase lock loop circuit as claimed in claim 1, wherein said means for comparing comprises: means for generating a first pulse for a first predetermined portion of said waveform-shaped data pulse; and means for producing a second pulse for a second predetermined portion of said waveform-shaped data pulses.

Claim 4

A digital phase lock loop circuit as claimed in claim 2, wherein said means for producing said phase control pulse includes: a first flip-flop for detecting whether or not the leading edge of said delayed reference clock pulse is present in said first predetermined portion of said waveform-shaped data pulse; and a second flip-flop for detecting whether or not the leading edge of said delayed reference clock pulse is present in said second predetermined portion of said waveform-shaped data pulses.

Claim 5

A digital phase lock loop circuit as claimed in claim 3, wherein said means for generating said delayed reference clock pulse comprises: an up/down counter for changing its value based on the detection result obtained from said first and second flip-flops of said means for producing said phase control pulse; a delay line circuit having a plurality of taps, each of which provides a predetermined delay to said reference clock pulse provided by the reference clock generator; and a multiplexer for selecting a tap, of said delay line circuit corresponding to the value in said up/down counter.

Claim 6

A digital phase lock loop circuit as claimed in claim 1, wherein the clock frequency of said clock pulse from the generator has a frequency of twice the frequency of said raw data pulses received from said external device.

Claim 7

A digital phase lock loop circuit comprising: a reference clock generator having a clock frequency higher than the frequency of raw data pulses received from an external device; a pulse shaper including means for subjecting each of said data pulses to waveform-shaping to obtain waveform-shaped pulses have pulse widths approximately equal to one clock period of said reference clock pulse; means for generating a first pulse for a first predetermined portion of said waveform-shaped data pulses; means for producing a second pulse for a second predetermined portion of said waveform-shaped data pulses; a phase comparator having a first flip-flop for detecting whether or not the leading edge of said delayed reference clock pulse is present during said first signal; a second flip-flop for detecting whether or not the leading edge of said delayed reference clock pulse is present during said second signal, whereby a phase control pulse is produced on the basis of the relative positions of said delayed reference clock pulse and each of said -waveform-shaped data pulses; and a phase shifter including an up/down counter for changing its value based on the detection result obtained from said first and second flip-flops, a delay line circuit having a plurality of taps, each of which provides a predetermined delay to said reference clock pulse provided by the reference clock generator, and a multiplexer for selecting a tap of the delay line circuit corresponding to the value of the up/down counter.

Claim 8

A digital phase lock loop circuit comprising: a reference clock generator having a clock frequency higher than the frequency of raw data pulses received from an external device; a pulse shaper including means for subjecting each of said data pulses to waveform-shaping to obtain waveform-shaped pulses have pulse widths approximately equal to one clock period of said reference clock pulse; means for generating a first pulse for a first predetermined portion of said waveform-shaped data pulses; means for producing a second pulse for a second predetermined portion of said waveform-shaped data pulses; a phase comparator having a first flip-flop for detecting whether or not the leading edge of said delayed reference clock pulse is present during said first signal; a second flip-flop for detecting whether or not the leading edge of said delayed reference clock pulse is present during said second signal, whereby a phase control pulse is produced on the basis of the relative positions of said delayed reference clock pulse and each of said -waveform-shaped data pulses; and a phase shifter including an up/down counter for changing its value based on the detection result obtained from said first and second flip-flops, a delay line circuit having a plurality of taps, each of which provides a predetermined delay to said reference clock pulse provided by the reference clock generator, and a multiplexer for selecting a tap of the delay line circuit corresponding to the value of the up/down counter.

Claim 9

A digital phase lock loop circuit for generating a corrected clock signal having a desired phase relationship with received data pulses having a repetition period, said circuit comprising: clock means for providing a plurality of clock signals phase-shifted with respect to one another; selection means for selecting as said corrected clock signal a desired one of said plurality of clock signals in accordance with a control signal; comparison means for comparing the relative positions of said corrected clock signal and said received data pulses and providing a comparison output; and control means responsive to said comparison output for generating said control signal.

Claim 10

A digital phase lock loop circuit for generating a corrected clock signal having a desired phase relationship with received data pulses having a repetition period, said circuit comprising: clock means for providing a plurality of clock signals phase-shifted with respect to one another; selection means for selecting as said corrected clock signal a desired one of said plurality of clock signals in accordance with a control signal; comparison means for comparing the relative positions of said corrected clock signal and said received data pulses and providing a comparison output; and control means responsive to said comparison output for generating said control signal.

Claim 11

A digital phase lock,loop circuit as claimed in claim 7, wherein said clock source means comprises a reference clock generator for generating a reference clock having a reference clock rate, and delay means receiving said reference clock and providing a plurality of clock outputs at respective taps, each of said plurality of clock outputs being phase-shifted with respect to one another.

Claim 12

A digital phase lock loop circuit as claimed in claim 7, wherein said control means comprises an up/down counter for increasing or decreasing a count value in accordance with said comparison output, said up/down counter providing as said control signal a counter output corresponding to the value in said counter.

Claim 13

A digital phase lock loop circuit as claimed in claim 7, wherein said comparison means comprises: pulse-shaping means for generating a first signal during a first portion of said repetition period of said received data pulses and a second signal during a second predetermined portion of said repetition period, and a phase comparator for generating as said comparison output a first comparison signal when a leading edge of said clock signal occurs during said first signal and generating a second comparison signal when a leading edge of said clock signal occurs during said second signal.

Claim 14

A digital phase lock loop circuit as claimed in claim 10, wherein said control means comprises a counter for incrementing or decrementing its counter value in response to said first or second comparison signal, respectively, said counter providing as said control signal a counter output representing said counter value.

Claim 15

A digital phase lock loop circuit as claimed in claim 10, wherein said pulse shaping means further comprises waveform-shaping means responsive to each received data pulse for generating a waveform-shaped data pulse having a duration substantially equal to a period of said corrected clock signal, and wherein said comparison means includes means for synchronizing said waveform-shaped data pulses to said corrected clock signals.