improvements in or relating to sample-and-hold circuits

Abstract

Abstract A sample-and-hold circuit (10) includes a correction capacitor, (C c ), a coupling capacitor (C cc ), and a primary holding capacitor C H ) connected serially between two ground points. The common node of the coupling capacitor and the holding capacitor is a held signal node (12). The common node of the coupling capacitor (C cc ) and the correction capacitor (C c ) is a correction voltage node (20). The circuit output is from the signal node (12) through a buffer (14) and a stage selecting switch (S F ). The output is-fed back to an operational amplifier (18) whose output is connected to the correction node (20) through a correction sampling switch (S c ). A switched (S A ) feedback loop connects the output of the amplifier 18 to the inverting input port. The primary signal input (IN) is to the signal node (12) through a primary sampling switch (S s ). The noninverting input (+) of the amplifier (26) is connected to the output of a buffer (22). The input of the buffer (22) receives the input signal through an input switch (S 1 ) and is also connected to an input capacitor (C,), which has its other side grounded.

Inventors

• 👤 Eric John Swanson

Bibliographic Details