Data error detection and correction circuit

Claim 2

A data error detection and correction circuit for detecting and correcting data errors in a group of data using Reed-Solomon codes characterized by the provision of: (a) memory means for storing said group of data; (b) a syndrome calculation circuit for producing syndromes Si (i is a positive integer) from said group of data; (c) an internal data bus; (d) first data conversion means for converting data on said internal data bus into logarithmic data; (e) multiplier-divider means for making operation of the data on said internal data bus by addition and subtraction operations of said logarithmic data; (f) second data conversion means for antilogarithmically converting data from said multiplier-divider means; (g) addition and subtraction means for making operation of the data from said second data conversion means and supplying resulted operated data to said internal data bus; (h) a first error detection circuit for detecting whether a single error exists in said group of data in accordance with said syndromes and said resulted operated data on said internal data bus to generate a first error detection signal by means of determinations whether S1·S1 = S0·S2, S2·S2 = S1·S3, S1 ≠0, S2 ≠ 0, S3 ≠0 and S4 ≠ 0; (i) a first error location detection circuit for detecting a location where the single error exists at the time said first error detection circuit detects the single error and producing a first error location signal; (j) address control means for addressing said memory means in accordance with said first error detection signal and said error location signal to read an error data therefrom; and (k) a data correction circuit for adding one of said syndromes on said internal data bus to said error data outputted from said memory means to thereby produce corrected data against said error data.

Claim 3

A data error detection and correction circuit according to claim 1, wherein said multiplier-divider means comprises a first delay circuit for delaying an output from said first data conversion means, and an addition circuit for adding an output from said first delay circuit to the output from said first data conversion means; and said addition and subtraction means comprises a second delay circuit for delaying an output from said second data conversion means, and an addition circuit for adding an output from said second delay circuit to the output from said second data conversion means; said multiplier-divider means outputting data log(S1·S1) and log(S0·S2) sequentially in this order based on the syndromes Sl, Sl, SO and S2 sequentially supplied in this order to said first data conversion means; said addition and subtraction means outputting data S1·S1 + SOoS2 based on sequential outputs S1·S1 and S0·S2 of said second data conversion means to which outputs log(S1·S1) and log(S0·S2) are sequentially applied from said multiplier-divider means; said multiplier-divider means further outputting data log(S2·S2) and log(S1·S3) sequentially in this order based on the syndromes S2, S2, Sl, and S3 sequentially supplied in this order to said first data conversion means; and said addition and subtraction means further outputting data S2·S2 + S1·S3 based on sequential outputs S2·S2 and S1-S3 of said second data conversion means to which outputs log(S2·S2) and log(S1·S3) are sequentially applied from said multiplier-divider means; and wherein said first error detection circuit determines whether the syndromes S0, Sl, S2, and S3 from said syndrome calculation circuit and the values S1·S1 + S0·S2 and S2-S2 + S1·S3 are zero and generating the first error detection signal when the syndromes S0, Sl, S2, and S3 are not zero and the values S1·S1 + SOoS2 and S2·S2 + S1·S3 are zero.

Claim 4

A data error detection and correction circuit for detecting and correcting data errors in a group of data using Reed-Solomon codes characterized by the provision of: (a) memory means for storing said group of data; (b) a syndrome calculation circuit for producing syndromes Si (i is a positive integer) from said group of data; (c) an internal data bus; (d) first data conversion means for converting data on said internal data bus into logarithmic data; (e) multiplier-divider means for making operation of the data on said internal data bus by addition and subtraction operations of said logarithmic data; (f) second data conversion means for antilogarithmically converting data from said multiplier-divider means; (g) addition and subtraction means for making operation of the data from said second data conversion means and supplying resulted operated data to said internal data bus; (h) a second error detection circuit for detecting whether double errors exist in said group of data in accordance with the output data of said multiplier-divider means and said second data conversion means by means of determinations whether (S1·S2 + S0·S3)/(S1·S1 + S0·S2) =α k + α ℓ , (S2·S2 + S1·S3)/(S1·S1 + SO.S2) = α k · α ℓ , wherein k and ℓ are zero or positive integers, said second error detection circuit generating a second error detection signal and a second error location signal when double errors are detected; (i) address control means for addressing said memory means in accordance with said second error detection signal and said second error location signal to read error data therefrom; and (j) a data correction circuit for adding data fed from said internal data bus representing data errors to said error data read from said memory means, respectively, to thereby produce corrected data against said error data.

Claim 5

A data error detection and correction circuit for detecting and correcting data errors in a group of data using Reed-Solomon codes characterized by the provision of: (a) memory means for storing said group of data; (b) a syndrome calculation circuit for producing syndromes Si (i is a positive integer) from said group of data; (c) an internal data bus; (d) first data conversion means for converting data on said internal data bus into logarithmic data; (e) multiplier-divider means for making operation of the data on said internal data bus by addition and subtraction operations of said logarithmic data; (f) second data conversion means for antilogarithmically converting data from said multiplier-divider means; (g) addition and subtraction means for making operation of the data from said second data conversion means and supplying resulted operated data to said internal data bus; (h) a second error detection circuit for detecting whether double errors exist in said group of data in accordance with the output data of said multiplier-divider means and said second data conversion means by means of determinations whether (S1·S2 + S0·S3)/(S1·S1 + S0·S2) =α k + α ℓ , (S2·S2 + S1·S3)/(S1·S1 + SO.S2) = α k · α ℓ , wherein k and ℓ are zero or positive integers, said second error detection circuit generating a second error detection signal and a second error location signal when double errors are detected; (i) address control means for addressing said memory means in accordance with said second error detection signal and said second error location signal to read error data therefrom; and (j) a data correction circuit for adding data fed from said internal data bus representing data errors to said error data read from said memory means, respectively, to thereby produce corrected data against said error data.

Claim 6

A data error detection and correction circuit according to claim 3, wherein said multiplier-divider means comprises a first delay circuit for delaying an output from said first data conversion means, and an addition circuit for adding an output from said first delay circuit to the output from said first data conversion means; and said addition and subtraction means comprises a second delay circuit for delaying an output from said second data conversion means, and an addition circuit for adding an output from said second delay circuit to the output from said second data conversion means; said multiplier-divider means outputting data log(S1·S1) and log(S0·S2) sequentially in this order based on the syndromes Sl, Sl, S0, and S2 sequentially supplied in this order to said first data conversion means; said addition and subtraction means outputting data S1·S1 + S0·S2 based on sequential outputs Sl-Sl and S0·S2 of said second data conversion means to which outputs log(S1·S1) and log(S0·S2) are sequentially applied from said multiplier-divider means; said multiplier-divider means further outputting data log(S2·S2) and log(S1·S3) sequentially in this order based on the syndromes S2, S2, Sl, and S3 sequentially supplied in this order to said first data conversion means; said addition and subtraction means further outputting data S2·S2 + S1·S3 based on sequential outputs S2·S2 and S1·S3 of said second data conversion means to which outputs log(S2 ' S2) and log(S1·S3) are sequentially applied from said multiplier-divider means; said multiplier-divider means further outputting data log(S1·S2) and log(S0·S3) sequentially in this order based on the syndromes Sl, S2, SO and S3 sequentially supplied in this order to said first data conversion means; said addition and subtraction means further outputting data S1·S2 + S0·S3 based on sequential outputs Sl-S2 and S0·S3 of said second data conversion means to which outputs log(S1·S2) and log(S0·S3) are sequentially applied from said multiplier-divider means; and said multiplier-divider means further outputting data log(S1·S2 + S0·S3)/(S1·S1 + SO-S2) and log(S2·S2 + S1·S3)/(S1·S1 + SO-S2) based on the output data Sl-Sl + S0·S2, S2·S2 + S1·S3, and S1·S2 + SO-S3 from said addition and subtraction means; and wherein said second error detection circuit comprises a circuit for obtaining a set of zero or integers k and ℓ in which k + ℓ = B and B = log(S2·S2 + S1·S2)/(S1·S1 + SO-S2), a data conversion circuit for antilogarithmically converting the data k and ℓ into data α k and α ℓ , respectively, an addition circuit for obtaining a value C A =α A + α k + α ℓ in which α A = (S1·S2 + S0·S3)/(S1·S1 + SO·S2) which is outputted from said second data conversion means, and a zero detection circuit for determining whether the value CA is zero and generating the second error detection signal and the second error location signal when the value CA is zero.

Claim 7

A data error detection and correction circuit according to claim 4, wherein said circuit for obtaining a set of k and ℓ of said second error detection circuit comprises first means for obtaining a value ℓ= B/2 + 1 based on the value B from said multiplier-divider means, and second means for obtaining a value k = B - ℓ based on the value B from said multiplier-divider means and the value ℓ from said first means; and said second error detection circuit further comprises means for making increment of the number ℓ and reactuating said second error detection circuit.