Patent US311898A successfully refreshed from Google Patents.
Patent EP0139266A2 successfully refreshed from Google Patents.
EP0139266A2
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EP
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A semiconductor integrated circuit device comprising an MOS transistor and a bipolar transistor and a manufacturing method of the same
Assignee: Toshiba Corp
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Filing: 1984-10-03
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Granted: —
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Expires: 2004-10-03
Abstract
Abstract A semiconductor integrated circuit device is disclosed which comprises a bipolar transistor and a field effect transistor, in which a gate electrode (38, 39) of the field effect transistor and a collector electrode (40<sub>2</sub>) of the bipolar transistor are formed from a common electrode layer (102) of a high impurity concentration, and in which the collector region (24<sub>2</sub>) of the bipolar transistor comprises a region (100) of a high impurity concentration having a conductivity type the same as that of the collector region (24<sub>2</sub>) of the bipolar transistor.
Inventors
- 👤 Hiroshi C/O Patent Division Iwasaki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 15:06
CPC Classifications
H; H10; H10P; H10P32/00; H10P32/10; H10P32/17; H10P32/171; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; H10P32/14; H10P32/1408; H10P32/1414; Y; Y10; Y10S; Y10S148/00; Y10S148/01; Y10S148/032; Y10S148/037; Y10S148/038; Y10S148/082; Y10S148/123; Y10S148/124
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
86 words
A semiconductor integrated circuit device comprising a bipolar transistor and a field effect transistor in which a gate electrode (38, 39) of the field effect transistor and a collector electrode (40 2 ) of the bipolar transistor are formed from a common - electrode layer (102) of a high impurity concentration, and in which the collector leading region (100) of the bipolar transistor comprises a region of a high impurity concentration having a conductivity type equal to that of the collector region of the bipolar transistor.
Claim 2
Dependent Claim
86 words
A semiconductor integrated circuit device comprising a bipolar transistor and a field effect transistor in which a gate electrode (38, 39) of the field effect transistor and a collector electrode (40 2 ) of the bipolar transistor are formed from a common - electrode layer (102) of a high impurity concentration, and in which the collector leading region (100) of the bipolar transistor comprises a region of a high impurity concentration having a conductivity type equal to that of the collector region of the bipolar transistor.
Claim 3
Dependent Claim
76 words
A semiconductor integrated circuit device according to claim 1, characterized in that said integrated circuit device comprises an embedded semiconductor region (24 1r 24 2 ) and a well region (26 1 , 26 2 ) formed in the semiconductor region, said bipolar transistor being formed in said well region, and said collector leading region extends in the direction of thickness of the embedded region to the PN junction defined between said well and embedded region.
Claim 4
Dependent Claim
22 words
A semiconductor integrated circuit device according to claim 1, characterized in that said field effect transistor is a metal oxide semiconductor transistor.
Claim 5
Dependent Claim
29 words
A semiconductor integrated circuit device according to claim 1, characterized in that there are comprised two of said metal oxide semiconductor transistors, the transistors being of complementary channel type.
Claim 6
Dependent Claim
26 words
A semiconductor integrated circuit device according to claim 1, characterized in that said common electrode layer is made of a polysilicon of a high impurity concentration.
Claim 7
Independent Claim
213 words
A method of manufacturing a semiconductor -integrated circuit device comprising: a step of forming a first semiconductor region (24 1 , 24 2 ) on a semiconductor substrate (23) of a first conductivity type, the first semiconductor region being of a second conductivity type and having a high impurity concentration; a step of forming a second semiconductor region (25) of said first conductivity type on said semiconductor substrate; a step of forming a third semiconductor region (261, 26 2 ) of said second conductivity type in said second semiconductor region, the third semiconductor region being electrically connected to said first semiconductor region; a step of forming a field effect transistor in said second or third semiconductor region, the step of forming the field effect transistor comprising a step of forming gate electrodes (38, 39) of the field effect transistor and the emitter and collector electrodes (40 1 , 40 2 ) of the bipolar transistor; a step of forming a bipolar transistor in said third semiconductor region; and a step of forming a fourth semiconductor region (100) of said second conductivity type in said third semiconductor region, using said collector electrode of the bipolar transistor as an impurity concentration region, the fourth semiconductor region having a high impurity concentration and a large thickness.
Claim 8
Independent Claim
213 words
A method of manufacturing a semiconductor -integrated circuit device comprising: a step of forming a first semiconductor region (24 1 , 24 2 ) on a semiconductor substrate (23) of a first conductivity type, the first semiconductor region being of a second conductivity type and having a high impurity concentration; a step of forming a second semiconductor region (25) of said first conductivity type on said semiconductor substrate; a step of forming a third semiconductor region (261, 26 2 ) of said second conductivity type in said second semiconductor region, the third semiconductor region being electrically connected to said first semiconductor region; a step of forming a field effect transistor in said second or third semiconductor region, the step of forming the field effect transistor comprising a step of forming gate electrodes (38, 39) of the field effect transistor and the emitter and collector electrodes (40 1 , 40 2 ) of the bipolar transistor; a step of forming a bipolar transistor in said third semiconductor region; and a step of forming a fourth semiconductor region (100) of said second conductivity type in said third semiconductor region, using said collector electrode of the bipolar transistor as an impurity concentration region, the fourth semiconductor region having a high impurity concentration and a large thickness.
Claim 9
Dependent Claim
25 words
A manufacturing method according to claim 6, characterized in that said gate electrodes are made of polysilicon diffused with an impurity in a high concentration.
Claim 10
Dependent Claim
20 words
A manufacturing method according to claim 6, characterized in that said fourth semiconductor region extends to said first semiconductor region.
Claim 11
Dependent Claim
20 words
A manufacturing method according to claim 7, characterized in that said fourth semiconductor region -extends to said first semiconductor region.
Claim 12
Dependent Claim
28 words
A manufacturing method according to claim 6, characterized in that the emitter region of said bipolar transistor is formed using an polysilicon layer as an impurity diffusion source.
Claim 13
Dependent Claim
28 words
A manufacturing method according to claim 7, characterized in that the emitter region of said bipolar transistor is formed using an polysilicon layer as an impurity diffusion source.
Claim 14
Dependent Claim
28 words
A manufacturing method according to claim 8, characterized in that the emitter region of said bipolar transistor is formed using an polysilicon layer as an impurity diffusion source.
Claim 15
Dependent Claim
28 words
A manufacturing method according to claim 9, characterized in that the emitter region of said bipolar -transistor is formed using an polysilicon layer as an impurity diffusion source.
References Cited (Backward Citations)
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