Patent EP0139196A2 successfully refreshed from Google Patents.
EP0139196A2
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Semiconductor memory having charge transfer device voltage amplifier
Assignee: Hitachi Ltd
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Filing: 1984-09-06
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Granted: —
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Expires: 2004-09-06
Abstract
Abstract A semiconductor memory includes a large number of memory cells arrayed in the shape of a matrix. A writing circuit (31), a voltage amplifier (32) and a sense amplifier (28) are successively connected to a data line (24,25) that connects input and output ends of the memory cells in an identical row. The voltage amplifier (32) is a charge transfer type voltage amplifier including two charge transfer gates and a driving gate located between them.
Inventors
- 👤 Masakazu Aoki
- 👤 Yoshinopbu Nakagome
- 👤 Masashi Horiguchi
- 👤 Toshifumi Ozaki
- 👤 Katsuhiro Shimohigashi
- 👤 Shinichi Ikenaga
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 09:15
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C7/00; G11C7/22; G11C7/06; H; H10; H10B; H10B12/00
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
231 words
A semiconductor device comprising memory arrays each including a plurality of memory cells that store charge carriers within a semiconductor as information sources, address means (26, 27) for appointing positions of the respective memory cells, data lines (24, 25; 44) connected to the memory cells to transfer the charge carriers as the information sources, and means (31) for writing information and means (32, 28; 50) for reading out the information as are connected to said data lines; characterised in that the reading-out means includes a reset gate transistor (45) having one terminal connected to said data line (44), a charge transfer portion, a precharge gate transistor (49) at an output end of said charge transfer portion, and a signal amplifier (sense amplifier 50), said charge transfer portion including two charge transfer gates (46, 48) and a driving gate (47) disposed between them; that the writing means (31) is arranged between the memory cell array and said charge transfer portion; and that another terminal of said reset gate transistor (45) is connected to means for applying a voltage which is lower, for electrons used as the information sources, or higher, for holes used as them, than a magnitude obtained by subtracting the threshold voltage of the charge transfer gate (46) on the data line side from a highest value of a voltage applied to said charge transfer gate (46). (Figs. 3, 5A)
Claim 2
Dependent Claim
231 words
A semiconductor device comprising memory arrays each including a plurality of memory cells that store charge carriers within a semiconductor as information sources, address means (26, 27) for appointing positions of the respective memory cells, data lines (24, 25; 44) connected to the memory cells to transfer the charge carriers as the information sources, and means (31) for writing information and means (32, 28; 50) for reading out the information as are connected to said data lines; characterised in that the reading-out means includes a reset gate transistor (45) having one terminal connected to said data line (44), a charge transfer portion, a precharge gate transistor (49) at an output end of said charge transfer portion, and a signal amplifier (sense amplifier 50), said charge transfer portion including two charge transfer gates (46, 48) and a driving gate (47) disposed between them; that the writing means (31) is arranged between the memory cell array and said charge transfer portion; and that another terminal of said reset gate transistor (45) is connected to means for applying a voltage which is lower, for electrons used as the information sources, or higher, for holes used as them, than a magnitude obtained by subtracting the threshold voltage of the charge transfer gate (46) on the data line side from a highest value of a voltage applied to said charge transfer gate (46). (Figs. 3, 5A)
Claim 3
Dependent Claim
18 words
The device of claim 1, wherein said sense amplifier (28; 50) is an amplifier which detects a voltage.
Claim 4
Independent Claim
43 words
The device of claim.1 or 2, wherein a capacitance C of an input end of said sense amplifier (50) is related to a capacitance C D of said data line (44) and a capacitance C of the charge driving gate (47) as follows:
Claim 5
Dependent Claim
209 words
A semiconductor device comprising memory arrays each including a plurality of memory cells that store charge carriers within a semiconductor as information sources, address means (26, 27) for appointing positions of the respective memory cells, data lines (24, 25; 44) connected to the memory cells to transfer the charge carriers as the information sources, and means (31) for writing information and means (32, 28; 50) for reading out the information as are connected to said data lines; characterised in that the reading-out means includes a reset gate transistor (45) connected to said data line (44), a charge transfer portion, a precharge gate transistor (49) at an output end of-said charge transfer portion, and a signal amplifier (sense amplifier 50), said charge transfer portion including two charge transfer gates (46, 48) and a driving gate (47) disposed between them; and that the threshold voltage V ThT1 of the charge transfer gate (46) on the data line side, the threshold voltage (V ThT2 ) of said driving gate (47) and the threshold voltage V ThT3 of the charge transfer gate (48) on the sense amplifier side are selected as: in case of transferring electrons as the information charge carriers, or as: in case of transferring holes as the information charge carriers.
Claim 6
Dependent Claim
209 words
A semiconductor device comprising memory arrays each including a plurality of memory cells that store charge carriers within a semiconductor as information sources, address means (26, 27) for appointing positions of the respective memory cells, data lines (24, 25; 44) connected to the memory cells to transfer the charge carriers as the information sources, and means (31) for writing information and means (32, 28; 50) for reading out the information as are connected to said data lines; characterised in that the reading-out means includes a reset gate transistor (45) connected to said data line (44), a charge transfer portion, a precharge gate transistor (49) at an output end of-said charge transfer portion, and a signal amplifier (sense amplifier 50), said charge transfer portion including two charge transfer gates (46, 48) and a driving gate (47) disposed between them; and that the threshold voltage V ThT1 of the charge transfer gate (46) on the data line side, the threshold voltage (V ThT2 ) of said driving gate (47) and the threshold voltage V ThT3 of the charge transfer gate (48) on the sense amplifier side are selected as: in case of transferring electrons as the information charge carriers, or as: in case of transferring holes as the information charge carriers.
Claim 7
Dependent Claim
15 words
The device of claim 4, wherein said driving gate (47) is of a depletion type.
Claim 8
Dependent Claim
62 words
The device of claim 4 or 5, wherein threshold voltages are selected as: in the case of transferring the electrons as the charge carriers, or as: in the case of transferring the holes as the charge carriers, wherein V φH denotes a hiqh level and V φL denotes a low level of a pulse which is impressed on said charge transfer portion.
References Cited (Backward Citations)
No citation records indexed.
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