Patent EP0139185A2 successfully refreshed from Google Patents.
EP0139185A2
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A high speed memory device and a method therefor
Assignee: Exel Microelectronics Inc
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Filing: 1984-08-30
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Granted: —
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Expires: 2004-08-30
Abstract
Abstract The present invention relates to a method and an apparatus for an improved electrically programmable read only memory device. Each device comprises a plurality of addressable bits with each bit having two storage cells. If one of the storage cells is charged and the other is uncharged, then the bit is in one logical state; if the one cell is uncharged and the other is charged, then the bit is in the other logical state. Voltage from the storage cells are detected differentially. As a result, greater speed in readout of the device can be achieved.
Inventors
- 👤 Richard Joseph Zeman
- 👤 Anil Gupta
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 08:55
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/28; G11C16/04; G11C16/0408; G11C16/0441
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
163 words
A method of operating a memory device having a plurality of addressable storage cells, each cell for storing a first amount of electrical charge anti for storing a second amount of electrical charge, said first amount different from said second amount, said method comprising the steps of: forming a plurality of paired cells; storing a first amount of electrical charge in one of the paired cells and a second amount of electrical charge in the other of the paired cells to represent a first logical state of said paired cell; or a second amount of electrical charge in one of the paired cells and a first amount of electrical charge in the other of the paired cells to represent a second logical state of said paired cell; and differentially sensing non-destructively the voltage from the one cell and the voltage from the other cell from each paired cell; whereby said differentially sensed voltage is indicative of the logical state of said paired cell.
Claim 2
Independent Claim
163 words
A method of operating a memory device having a plurality of addressable storage cells, each cell for storing a first amount of electrical charge anti for storing a second amount of electrical charge, said first amount different from said second amount, said method comprising the steps of: forming a plurality of paired cells; storing a first amount of electrical charge in one of the paired cells and a second amount of electrical charge in the other of the paired cells to represent a first logical state of said paired cell; or a second amount of electrical charge in one of the paired cells and a first amount of electrical charge in the other of the paired cells to represent a second logical state of said paired cell; and differentially sensing non-destructively the voltage from the one cell and the voltage from the other cell from each paired cell; whereby said differentially sensed voltage is indicative of the logical state of said paired cell.
Claim 3
Dependent Claim
17 words
The method of Claim 1 wherein said memory device is an Electrically Erasable Programmable Read Only Memory.
Claim 4
Dependent Claim
19 words
The method of Claim 2 wherein each of said storage cells is a storage transistor having a floating gate.
Claim 5
Dependent Claim
16 words
The method of Claim 2 wherein said first amount is greater than said second amount. \
Claim 6
Dependent Claim
40 words
The method of Claim 4 wherein said storing step further comprises: storing a first amount in said one cell and said other cell; and discharging said one or said other cell to reduce the charge therein to the second amount.
Claim 7
Dependent Claim
16 words
The method of Claim 1 wherein said memory device is an Electrically Programmable Read Only Memory.
Claim 8
Dependent Claim
19 words
The method of Claim 6 wherein each of said storage cells is a storage transistor having a floating gate.
Claim 9
Dependent Claim
20 words
The method of Claim 6 wherein said first amount is greater than said second amount, which is substantially near zero.
Claim 10
Dependent Claim
48 words
The method of Claim 8 wherein said storing step further comprises: exposing each cell to ultra-violet electromagnetic radiation to reduce the charge therein to the second amount; and charging said one or said other cell of each paired cell to increase the charge therein to the first amount.
Claim 11
Independent Claim
166 words
A method of storing electrical charges in a memory device having a plurality of bits, each bit representative of a first or a second logical state and for reading said state therefrom, said memory device having a plurality of storage transistors, means for addressing each transistor for storing electrical charge therein and means for non-destructively reading the amount of charge stored in each transistor: said method comprising the steps of: forming a plurality of bits, each bit being a pair of storage transistors, each pair having a first and a second transistor; charging both of said transistors in each bit; discharging only one of said transistors in each bit; discharging the first transistor for representing the first logical state for said bit or discharging the second transistor for representing the second logical state for said bit; and non-destructively sensing differentially the amount of voltage from the first and the second transistors; whereby the amount of differential voltage is representative of the logical state of each bit.
Claim 12
Independent Claim
166 words
A method of storing electrical charges in a memory device having a plurality of bits, each bit representative of a first or a second logical state and for reading said state therefrom, said memory device having a plurality of storage transistors, means for addressing each transistor for storing electrical charge therein and means for non-destructively reading the amount of charge stored in each transistor: said method comprising the steps of: forming a plurality of bits, each bit being a pair of storage transistors, each pair having a first and a second transistor; charging both of said transistors in each bit; discharging only one of said transistors in each bit; discharging the first transistor for representing the first logical state for said bit or discharging the second transistor for representing the second logical state for said bit; and non-destructively sensing differentially the amount of voltage from the first and the second transistors; whereby the amount of differential voltage is representative of the logical state of each bit.
Claim 13
Dependent Claim
134 words
A memory device comprising: a plurality of storage cells, each cell having a first and a second storage transistor means, each transistor means for storing electrical charge of a first amount or of a second amount; each cell for storing charge of a first amount in the first transistor means and charge of a second amount in the second transistor means for representing a first logical state of said cell or for storing charge of a second amount in the first said transistor means and charge of a first amount in the second transistor means for representing a second logical state of said cell; and means for differentially sensing non-destructively the voltage from the two transistor means from each cell; whereby the differentially sensed voltage is representative of the logical state of said cell.
Claim 14
Dependent Claim
134 words
A memory device comprising: a plurality of storage cells, each cell having a first and a second storage transistor means, each transistor means for storing electrical charge of a first amount or of a second amount; each cell for storing charge of a first amount in the first transistor means and charge of a second amount in the second transistor means for representing a first logical state of said cell or for storing charge of a second amount in the first said transistor means and charge of a first amount in the second transistor means for representing a second logical state of said cell; and means for differentially sensing non-destructively the voltage from the two transistor means from each cell; whereby the differentially sensed voltage is representative of the logical state of said cell.
Claim 15
Dependent Claim
19 words
The device of Claim 11 wherein each storage transistor means is a storage transistor of the MOS FET type.
Claim 16
Dependent Claim
16 words
The device of Claim 12 wherein each transistor is an electrically erasable programmable read only transistor.
Claim 17
Dependent Claim
14 words
The device of Claim 12 wherein each transistor is an electrically programmable read-only transistor.
References Cited (Backward Citations)
No citation records indexed.
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