Communications network having a single node and a plurality of outstations

Claim 3

A method according to Claim 1, wherein each marker signal takes the form of preamble transmitted at the start of its burst, and also wherein said preamble comprises (a) bit synchronisation followed by; (b) byte synchronisation.

Claim 4

A method according to Claim 2, wherein the marker signals of bursts transmitted from node to terminal include the address of the destination and the marker signals of bursts from outstations to node include the address of the origin.

Claim 6

A method according to Claim 4 wherein the node: a) checks the synchronisation of received bursts; b) produces error signals indicating the extent of any errors; c) transmits said error signals to the originating outstations.

Claim 7

A method according to Claim 5 wherein the outstations change their standardised delays in accordance with received error signals whereby the node keeps correct synchronisation of its received signals.

Claim 9

A method according to Claim 7 wherein said identification takes the form of distinctive byte synchronisation.

Claim 13

A node suitable for participating in a method according to any one of the preceding Claims, which node comprises:- (a) means for receiving traffic for a plurality of outstations and dividing said traffic into portions suitable for transmission in a single burst; (b) means for producing bursts by combining said traffic portions with marker signals; (c) means for transmitting said bursts in sequence to said plurality of outstations; (d) means for receiving signals originating from said plurality of outstations, said signals being in the form of bursts wherein each burst includes marker signals; (e) means for identifying the received marker signals and synchronising the operation of (d) to the receipt of said marker.

Claim 14

A node according to Claim 12, which also includes means for comparing the times of arrival of received bursts with a specified schedule therefore and producing error signals indicative of discrepancies there between and means of transmitting said error signals to the outstations.

Claim 15

A node for participating in a method according to any one of claims 1 to 11 which node comprises: a) A transmitter for transmitting to a plurality of outstations; b) A receiver for receiving from said plurality of outstations; c) A plurality of terminal cards, each adapted to handle the traffic in a single slot, each of said cards beng connected (i) to receive demodulated data from the receiver and (ii) to pass data for transmission to the transmitter; d) A single system card, also connected to the receiver and the transmitter; and e) Supervisory means adapted to control the operating sequence of the terminal cards and the system card wherein the supervisory means is connected to the system card whereby the supervisory means can send system information and instructions to the outstations and also wherein in each terminal card comprises: c) (i) means for receiving traffic for its slot and dividing said traffic into portions suitable for transmission in a single slot; c) (ii) means for producing bursts by combining said traffic portions with marker signals comprising bit synchronisation and byte synchronisation; c) (iii)means for passing said bursts to the transmitter; c) (iv) means for receiving demodulated signals from the receiver; c) (v) timing means synchronisable with the frame period and adapted to actuate means c)(iv) . to operate in a pre-set phase of its own cycle; c) (vi) means for recognising preamble and adapted to adjust the set point of the timing means so that the preamble occurs at the correct phase of the cycle of the timing means c)(v).

Claim 16

An outstation suitable for participating in a process according to any one of Claims 1 to 11, which outstation comprises: a) means for receiving signals from a node, said signals taking the form of traffic combined with marker signals; b) timing means for identifying its own slot and selecting bursts contained therein c) means for receiving traffic for the node and dividing said traffic into portions suitable for transmission in a single slot; d) means for producing bursts by combining said portions with marker signals; e) means for transmitting said bursts to the node; f) means for synchronising functions a) to e) to the receipt of marker in its own slot.

Claim 17

An outstation according to Claim 15 which includes: a) a clock adapted to measure a pre-set delay; b) means to initiate said clock on receipt of a preamble in its own slot; c) means to initiate transmission means specified in part (e) of Claim 15 when said clock ends the measure of the pre-set delay.

Claim 18

An outstation according to Claim 16, which also includes: a) means for receiving error signals relating to the pre-set delay specified in part (a) of Claim 16, and (b) means for adjusting said pre-set delay in accordance with said error signals.

Claim 19

An outstation for participating in a method according to any one of Claims 1 to 11, which outstation comprises: a) a transmitter for transmitting to the node; b) a receiver for receiving from the node; c) one or more terminal cards, each adapted to handle the traffic in a single slot, each of said cards being connected to the receiver and the transmitter wherein each terminal card comprises: c) (i) means for receiving traffic for transmission in its slot and dividing said traffic into portions suitable for transmission in a single slot; c) (ii) means for producing bursts by combining said traffic portions with marker signals comprising bit synchronisation and byte synchronisation; c) (iii)means for passing said bursts to the transmitter; c) (iv) means for receiving demodulated signals from the receiver; c) (v) means for recognising preamble containing the address of the user and passing on traffic contained in bursts so identified. c) (vi) timing means synchronisable with the frame period and adapted to activate means c)(i) and c)(iv) in correct sequence and at pre-set phases in its own cycle; c) (vii)means for recognising preamble and adapted to adjust the set point of the timing means so that the preamble occurs at the correct phase of the cycle of the timing means.

Claim 20

Interface circuit for performing send-and-receive functions of a telecommunications station according to any one of claims 12 to 18 so as to synchronise said function with a specified slot of time multiplexed operation between a single node and a plurality of terminals, characterised in that the interface circuit comprises:- (a) enable means having first and second inputs and an output for synchronisation signals; (b) comparator means adapted to receive signals and connected to the first input of the enable means; (c) a cyclic timer adapted to receive a clock signal and to control the said send and receive functions to occur at preset phases of the cycle of the timer, said timer being connected to the second input of the enable means; (d) data capture means for receiving and retaining signal and operatively connected to receive synchronisation signals from the output of the enable means, said data capture means being adapted to initiate a data capture sequence on receipt of each synchronisation signal; (e) synchronisation means connected to receive synchronisation signals from the output of the enable means, said synchronisation means being adapted to produce an error signal measuring the discrepancy between the phase of the timer at which the synchronisation signal occurs and the predetermined phase of the cycle of the timer at which the synchronisation signal is supposed to occur; wherein: (i) said comparator means is adapted to compare received signal with a datum and to provide a coincidence signal to said first input of said enable means upon coincidences of said received signal with said datum, and (ii) said timer is adapted to define a synchronisation window and to provide an enable signal on said second input of said enable means during said time window; whereby the occurence within the time window of coincidences between the signal and the datum causes the enable means to provide a synchronisation signal.

Claim 21

An interface according to claim 19, wherein the comparator means comprises a shift register for received signals, a datum register for holding the datum and a bit comparator for comparing each bit of the shift register with the corresponding bit of the datum register and producing the coincidence signal when all bits match.

Claim 22

An interface according to either claim 19 or claim 20, wherein the data capture means comprises a shift register which is adapted to receive data in bit serial form and transfer means adapted to transfer said data to random access memory in bit parallel form using a transfer cycle having a period equal to the number of bits in a byte, said transfer means being connected to the enable means in such a manner that the reception of a synchronisation signal adjusts the phase of the transfer cycle so that the signal bit following the synchronisation signal is the first of a new byte.

Claim 23

Interface circuit according to any one of claims 19 to 21 which also comprises a burst generator for providing signal bursts for transmission, wherein said burst generator is operatively connected to the timer for the initiation of bursts at a preset phase of the timer.

Claim 24

Interface circuit according to any one of claims 19 to 22, which also comprises means for changing the operating slot of the interface, said means comprising means for changing the phase of the timer to correspond to the phase of the new slot and means for changing the contents of the datum store to correspond to the datum of the new slot.