Patent EP0138045A2 successfully refreshed from Google Patents.
EP0138045A2
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EP
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Apparatus and method for synchronization of peripheral devices via bus cycle alteration in a microprocessor implemented data processing system
Assignee: International Business Machines Corp
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Filing: 1984-09-10
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Granted: —
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Expires: 2004-09-10
Abstract
Abstract Synchronization of the operation of a peripheral (16) with that of a processor (12) in a multi-microprocessor implemented data processing system is achieved by bus cycle alteration. Logic circuit means (48, 62, 72) are provided for monitoring the condition of a peripheral's status bits (40, 42) and for preventing an appropriate processor control signal (80) from completing the present bus cycle if the peripheral of interest is not able to accept an access. The peripheral of interest (16) is readily identified by providing unique memory mapped locations (30), one for each system peripheral, that are responsively connected (18, 58, 56) to the logic circuit means (48).
Inventors
- 👤 Joseph P. Buonomo
- 👤 Raymond E. Losinger
- 👤 Burton L. Oliver
- 👤 Daniel J. Sucher
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 22:06
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4217
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
193 words
A method for synchronizing a peripheral device (16) and the host processor (12) of a data processing system (10) to which said peripheral device is coupled by means of a local or system bus (18, 22), said data processing system including means for generating a bus control signal (80) for use by said host processor, characterized by the steps of: a) providing a plurality of peripheral devices each of which is capable of generating at least one status signal (40, 42) indicative of its operational state, all of which peripherals are coupled to said data processing system bus; b) providing a unique memory mapped address (30) for each peripheral that is connected to said data processing system bus; c) detecting (58) accesses to any one of said unique memory mapped locations; d) monitoring (44, 46) said status signals of all peripheral devices; e) altering the current bus cycle of said system in response to the detection (48) of an access to one of said unique memory mapped locations if the status signal of an accessed peripheral device indicates that said peripheral cannot accept the access, by intercepting (72) said bus control signal (80).
Claim 2
Independent Claim
193 words
A method for synchronizing a peripheral device (16) and the host processor (12) of a data processing system (10) to which said peripheral device is coupled by means of a local or system bus (18, 22), said data processing system including means for generating a bus control signal (80) for use by said host processor, characterized by the steps of: a) providing a plurality of peripheral devices each of which is capable of generating at least one status signal (40, 42) indicative of its operational state, all of which peripherals are coupled to said data processing system bus; b) providing a unique memory mapped address (30) for each peripheral that is connected to said data processing system bus; c) detecting (58) accesses to any one of said unique memory mapped locations; d) monitoring (44, 46) said status signals of all peripheral devices; e) altering the current bus cycle of said system in response to the detection (48) of an access to one of said unique memory mapped locations if the status signal of an accessed peripheral device indicates that said peripheral cannot accept the access, by intercepting (72) said bus control signal (80).
Claim 3
Dependent Claim
21 words
The method according to claim 1 wherein said monitoring step is limited to monitoring the busy signal (40) of said peripherals.
Claim 4
Dependent Claim
21 words
The method according to claim 1 wherein said monitoring step is limited to monitoring the ready signal (42) of said peripherals.
Claim 5
Dependent Claim
23 words
The method according to claim 1 wherein said monitoring step is limited to monitoring both the busy and ready signals of said peripherals.
Claim 6
Dependent Claim
35 words
A method according to claim 3 or 4 wherein said detecting step (c) includes detecting (62) the invocation of a function of a peripheral if the ready signal (42) of said peripheral is not present.
Claim 7
Independent Claim
83 words
The method according to a previous claim wherein said step of altering the current bus cycle of said system, in response to the detection of an access to one of said unique memory mapped locations if the status signal of an accessed peripheral device indicates that said peripheral cannot accept the access, is directed to extending the current bus cycle so that said host processor (12) cannot start the next bus cycle until the accessed peripheral (16) is free to perform its function.
Claim 8
Dependent Claim
235 words
Apparatus for synchronizing a peripheral device (16) capable of generating at least one status signal (40) indicative of its operational state and the host processor (12) of a data processing system (10) to which said peripheral device is coupled by means of a local or system bus (18, 22), said data processing system including means for generating a bus control signal for use by said host processor, characterized by: a) a signal line (80) for carrying said bus control signal connected between said generating means and said host processor; b) a plurality of unique memory mapped addresses (30), one for each peripheral device connected to said data processing system bus; c) first logic circuit means (58, 70), connected to said plurality of memory mapped locations, for generating an access signal indicating that an access to one of said locations and its associated peripheral device has been attempted and/or its function is invoked; d) second logic circuit means (48, 62, 72), connected to said plurality of peripheral devices to receive status signals therefrom, to said first logic circuit means to receive access signals therefrom and to said signal line (80), for generating a bus control blocking signal to be applied to said signal line to alter the current bus cycle in response to receipt of a status signal indicating that a peripheral cannot accept an access and in response to an access signal for that peripheral.
Claim 9
Dependent Claim
235 words
Apparatus for synchronizing a peripheral device (16) capable of generating at least one status signal (40) indicative of its operational state and the host processor (12) of a data processing system (10) to which said peripheral device is coupled by means of a local or system bus (18, 22), said data processing system including means for generating a bus control signal for use by said host processor, characterized by: a) a signal line (80) for carrying said bus control signal connected between said generating means and said host processor; b) a plurality of unique memory mapped addresses (30), one for each peripheral device connected to said data processing system bus; c) first logic circuit means (58, 70), connected to said plurality of memory mapped locations, for generating an access signal indicating that an access to one of said locations and its associated peripheral device has been attempted and/or its function is invoked; d) second logic circuit means (48, 62, 72), connected to said plurality of peripheral devices to receive status signals therefrom, to said first logic circuit means to receive access signals therefrom and to said signal line (80), for generating a bus control blocking signal to be applied to said signal line to alter the current bus cycle in response to receipt of a status signal indicating that a peripheral cannot accept an access and in response to an access signal for that peripheral.
Claim 10
Dependent Claim
28 words
The apparatus according to claim 7 wherein said second logic circuit means (48) is adapted to respond to busy status signals (40) from said plurality of peripheral devices.
Claim 11
Dependent Claim
28 words
The apparatus according to claim 7 wherein said second logic circuit means (62) is adapted to respond to ready status signals (42) from said plurality of peripheral devices.
Claim 12
Dependent Claim
28 words
The apparatus according to claim 7 wherein said second logic circuit means is adapted to respond to busy and ready status signals from said plurality of peripheral devices.
References Cited (Backward Citations)
No citation records indexed.
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