Burst signal generator

Claim 2

A burst signal generator in which waveform data of one cycle are stored in a waveform memory (14) at fixed phase intervals; a value corresponding to the frequency of a burst signal to be generated is set in frequency setting means (11); the set value is accumulated by accumulating means (12, 13) upon each occurrence of a clock signal from a clock signal source (5); the waveform memory is read out, using the accumulated value as an address; and the waveform data read out of the waveform memory is converted by a D/A converter (16) into an analog signal-, characterized by the provision of: wave-number setting means for setting the number of waves of the burst signal to be generated; and wave-number detecting means (21, 22) for counting the number of times the waveform data of one cycle is read out from the waveform memory (14) and for generating a wave-number count end signal when the count value has reached the number of waves set in a wave-number setting means (22) provided in the wave-number detecting means

Claim 3

A burst signal generator according to claim 1, comprising end phase detecting means for counting the clock signals a given number of times and generating a phase count end signal, wherein the generation of the burst signal is stopped upon generation of the phase count end signal after the generation of the wave-number count end signal.

Claim 4

A burst signal generator according to claim 2, wherein the accumulating means comprises a cumulative adder for adding the output of the frequency setting means and the preceding output of the accumulating means and a latch circuit for latching therein the result of the addition upon each occurrence of the clock signal and outputting the result as the output of the accumulating means.

Claim 5

A burst signal generator according to claim .3, comprising a gate circuit connected to the output of the clock signal source for passing therethrough the clock signals; wherein the wave-number detecting means comprises a wave-number counter for counting the number of times the waveform data of one cycle is repeatedly readout of the waveform memory, and the end phase detecting means comprises a phase counter for counting the clock signals from the gate circuit and an end phase setting means for setting therein an end value corresponding to an end phase of the burst signal; and wherein the gate circuit is closed by the phase count end signal generated after the occurrence of the wave-number count end signal, thereby to stop the generation of the burst signal.

Claim 6

A burst signal generator according to claim 1, comprising start phase setting means for setting therein a start value corresponding to a start phase of the burst signal and means for adding the start value and the accumulated value of the accumulating means to provide the added value as a readout address for the waveform memory.

Claim 7

A burst signal generator according to claim 4, comprising gate means inserted between the output of the gate circuit and the phase counter, wherein the wave-number count end signal from the wave-number detecting means opens the gate means to pass therethrough the clock signals.

Claim 8

A burst signal generator according to claim 4, wherein the wave-number counter and the phase counter are both presettable counters; at the start of generation of the burst signal, the contents of the wave-number setting means and the end phase setting means are preset in the wave-number counter and the phase counter, respectively; upon detecting that all bits of the wave-number counter have assumed the same value, the wave-number detecting means outputs the wave-number count end signal; and upon detecting that all bits of the phase counter have assumed the same value, the end phase detecting means outputs the phase count end signal.

Claim 9

A burst signal generator according to claim 7, wherein the phase counter always counts the clock signals during the generation of the burst signal; the phase counter is preset upon each counting of the wave-number counter; and a circuit is provided which outputs a signal for closing the gate circuit, upon occurrence of the phase count end signal when the wave-number count end signal is being generated.

Claim 10

A burst signal generator according to claim 4, comprising start phase setting means for setting therein a start value corresponding to a start phase of the burst signal and selector means for selectively supplying the outputs of the cumulative adder and the start phase setting means to the latch circuit.

Claim 11

A burst signal generator according to claim 4, comprising start phase setting means for setting therein a start value corresponding to a start phase of the burst signal and means for adding the start value and the output of latch circuit to provide the added value as a readout address for the waveform memory.

Claim 12

A burst signal generator according to claim 9 or 10, comprising control means for setting the start value, the frequency value, the number of waves and the end value to the start phase setting means, the frequency setting means, the wave-number setting means and the end phase setting means, respectively.

Claim 13

A burst signal generator according to claim 11, wherein the control means generates a reset/preset command for resetting the latch circuit and presetting the contents of the wave-number setting means and the end phase setting means into the wave-number counter and the phase counter, respectively, and then a latch command for the latch circuit to perform an initial latch operation before permitting the clock signals to be applied to the latch circuit.

Claim 14

A burst signal generator according to claim 12, comprising signal generating means for generating a reset/preset signal and a latch signal in response to the reset/preset command and the latch command from the control means and applying a reset/preset signal to the latch circuit, the wave-number counter and the phase counter and then, a latch signal to the latch circuit.

Claim 15

A burst signal generator according to claim 11, wherein the clock signal source comprises an oscillator for generating a reference clock and a variable frequency divider for frequency dividing the reference clock to output the clock signal; the frequency dividing ratio of the variable frequency divider is determined by a frequency dividing ratio set in a frequency dividing ratio setting register; and the frequency dividing ratio of the frequency dividing ratio setting register is set by the control means.

Claim 16

A burst signal generator according to claim 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10, wherein the accumulating means yields a carry signal each time its accumulated value exceeds the number of waveform data in the waveform memory; and such carry signals are counted by the wave-number detecting means.

Claim 17

A burst signal generator according to claim 3, 4, 5, 6, 7, 8, 9 or 10, wherein the output of the cumulative adder having a bit length equal to that of a maximum address value of the waveform memory and one-half the set value of the frequency setting means are compared by a comparator, and by the comparator output indicating that the-former is greater than the latter, the phase counter is caused to output the stop signal when its count value becomes smaller than the preset phase value by one.

Claim 18

A burst signal generator according to claim 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10, comprising access-number detecting means including access-number setting means for setting therein the number of accesses with which one cycle of the readout of the waveform memory is to be completed, and an access-number counter for counting the clock signals, wherein the access-number detecting means generates a one cycle end signal each time the access-number counter counts the clock signals the number of times equal to the content of the access-number setting means, and the generated one cycle end signal is applied to the wave-number detecting means so as to be counted.

Claim 19

A burst signal generator according to claim 2, wherein there is provided control means including a CPU, a RAM, a ROM and the waveform memory, all connected to one another via a bus; predetermined first, second and third address areas of the RAM are used as the frequency setting means, wave-number setting means and the end phase setting means, respectively; the CPU is operative in-accordance with a program stored in the ROM: (a) to add the frequency value in the first address area and a content of a fourth address area of the RAM for storing the accumulated value and to store the added result as a new accumulated value in the fourth address area upon each detection of an interrupt by the clock signal, thereby implementing the accumulating means; (b) to decide if a carry is produced from a predetermined bit position in the addition performed by the accumulating means and, if so, to change the content of the second address area by one, and to decide if the content of the second address area becomes a predetermined value and, if so, to generate the wave-number count end signal, thereby implementing the wave-number detecting means; and (e) to change the content of the third address area by one upon detection of the wave-number count end signal, and to decide if the content of the third address area becomes a predetermined value and, if so, to generate the phase count end signal, thereby implementing the end phase detecting means.