Patent EP0136811B1 successfully refreshed from Google Patents.
EP0136811B1
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Bit line load and column circuitry for a semiconductor memory
Assignee: Thorn EMI North America Inc
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Filing: 1984-08-24
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Granted: 1990-06-13
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Expires: 2004-08-24
Abstract
No abstract record available.
Inventors
- 👤 Kim C. Hardee
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 23:39
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C5/147; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419; G11C7/00; G11C7/12
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
227 words
A CMOS integrated circuit device having a memory array; a plurality of pairs of column lines (14,16); a plurality of word lines (18); a plurality of multitransistor memory cells (12), each cell including a pair of cross coupled N-channel transistors and being located at an intersection of, and connected to, a pair of column lines and one said word line; and control circuitry (10) including a plurality of bias means each connected to a corresponding column line, each said bias means including a P-channel transistor (32) and an N-channel transistor (30) operating as a clamp, each transistor having its source-drain path coupled between a supply voltage and said corresponding column line, wherein each said bias means (10) is arranged to limit the voltage swing on the column line as the column line (14, 16) for the particular bias means is pulled toward ground; characterised in that the P-channel transistor is connected to operate as a current source and in that the control circuitry further includes a voltage reference circuit (VR1) connected to said supply voltage input (VCC) and having an output connected to the gates of said P-channel transistors (32) for each pair of said bias means connected to a pair of column lines, said reference circuit providing compensation means (96, 98, 100) for compensating the effects of variations in ambient conditions within the integrated circuit device.
Claim 2
Dependent Claim
227 words
A CMOS integrated circuit device having a memory array; a plurality of pairs of column lines (14,16); a plurality of word lines (18); a plurality of multitransistor memory cells (12), each cell including a pair of cross coupled N-channel transistors and being located at an intersection of, and connected to, a pair of column lines and one said word line; and control circuitry (10) including a plurality of bias means each connected to a corresponding column line, each said bias means including a P-channel transistor (32) and an N-channel transistor (30) operating as a clamp, each transistor having its source-drain path coupled between a supply voltage and said corresponding column line, wherein each said bias means (10) is arranged to limit the voltage swing on the column line as the column line (14, 16) for the particular bias means is pulled toward ground; characterised in that the P-channel transistor is connected to operate as a current source and in that the control circuitry further includes a voltage reference circuit (VR1) connected to said supply voltage input (VCC) and having an output connected to the gates of said P-channel transistors (32) for each pair of said bias means connected to a pair of column lines, said reference circuit providing compensation means (96, 98, 100) for compensating the effects of variations in ambient conditions within the integrated circuit device.
Claim 3
Dependent Claim
48 words
A CMOS integrated circuit device according to claim 1 wherein said compensation means in the voltage reference circuit comprise transistor elements (96, 98, 100) sized to mirror transistor elements of said bias means (10) and said memory cells (12) and thereby compensate for ambient conditions within said device.
Claim 4
Dependent Claim
57 words
A CMOS integrated circuit device according to any preceding claim wherein said voltage reference circuit comprises a first P-channel transistor (102) having its drain connected to a first source voltage and three connected N-channel transistors (96, 98, 100) having their source/drain paths coupled in series between the source of said first P-channel transistor and a reference potential.
Claim 5
Dependent Claim
30 words
A CMOS integrated circuit device according to claim 1 or 2 wherein said voltage reference circuit includes a self-biased inverter including a P-channel transistor (90) and an N-channel transistor (92).
Claim 6
Dependent Claim
42 words
A CMOS integrated circuit device according to claim 1 or 2 wherein said voltage reference circuit includes P-channel transistors and N-channel transistors to provide a first reference voltage which varies to compensate for changes in the ambient conditions within the semiconductor memory.
Claim 7
Dependent Claim
29 words
A CMOS integrated circuit device according to any preceding claim wherein each said memory cell comprises four N-channel transistors, two of which are connected in a cross-coupled latch circuit.
Claim 8
Dependent Claim
53 words
A CMOS integrated circuit device according to claim 3 wherein said first P-channel transistor (102) has its source-drain path coupled between the first source voltage (VCC) and said output of said voltage reference circuit, and the three N-channel transistors have their source-drain paths coupled in series between the reference potential and said output.
Claim 9
Dependent Claim
34 words
A CMOS integrated circuit device according to any preceding claim wherein said voltage reference circuit provides a non-zero voltage to the gate electrodes of said P-channel transistors (32) in said plurality of bias means.
Claim 10
Dependent Claim
135 words
A CMOS integrated circuit device according to any preceding claim wherein said semiconductor memory includes a pair of data read lines (24, 26) coupled to a plurality of pairs of column transistors (42, 44), each gated by a corresponding column line (14, 16) and each selectively coupling a respective data read line to a common node (60) between an associated pair of input transistors, whereby each column comprises a pair of column lines and has associated with it a respective common node selectively coupled to the data read lines; the column circuitry further comprising a current source load (48, 50) coupled to said data read lines and to a second voltage reference circuit (VR2) which provides a second reference voltage which varies to compensate for changes in the ambient conditions within the integrated circuit device.
Claim 11
Dependent Claim
74 words
A CMOS integrated circuit device according to claim 9 further comprising a plurality of sneak capacitance reduction means (66) each coupled between a respective pair of said column lines (14, 16) and being responsive to a column select signal (Yn) to couple the column line pair together to permit the memory cell therebetween to isolate said read lines from each of said common nodes (60) except for the common node in the selected column.
Claim 12
Dependent Claim
82 words
A CMOS integrated circuit device according to any of claims 1 to 8 having column circuitry comprising a pair of data read lines (24, 26) associated with a plurality of pairs of column lines and, for each column, a respective differential amplifier arrangement (46, 56, 52, 54) coupled to said data read lines and connected to a third voltage reference circuit which provides a third reference voltage which varies to compensate for changes in transistor characteristics due to variation in ambient temperature.
References Cited (Backward Citations)
No citation records indexed.
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