Patent EP0136538A2 successfully refreshed from Google Patents.
EP0136538A2
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EP
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Inter-element processor in a high performance parallel vector processor
Assignee: International Business Machines Corp
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Filing: 1984-08-29
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Granted: —
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Expires: 2004-08-29
Abstract
Abstract @ A parallel vector processor is disclosed. In order to increase the performance of the parallel vector processor, the present invention decreases the time required to process the elements of a single vector stored in a vector register (121. Each vector register of a plurality of vector registers is subdivided into a plurality of smaller registers (12a). A vector, stored in a vector register (12), comprises N elements; however, each of the smaller registers (12a) stores M elements of the vector, where M is less than N. An element processor (20) is associated with each smaller register for processing the M elements of the vectors stored in the smaller register and storing a result of the processing in a result register. Each of the smaller registers of the vector registers, and its corresponding element processor, comprise a unit (30). A plurality of units (30) are connected in a parallel configuration. The element processors, associated with each unit, have been loaded with the result, the result being stored in a result register. Each of the results are processed in parallel fashion, as a result of the parallel configuration of the plurality of units. Therefore, the time required to process the elements of a single vector, stored in a vector register, is decreased.
Inventors
- 👤 Chuck H. Ngai
- 👤 Edward R. Wassel
- 👤 Gerald J. Watkins
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 15:15
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/3001; G06F9/30014; G06F15/00; G06F15/76; G06F15/80; G06F15/8053; G06F15/8076; G06F9/30036
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
146 words
A vector processor, comprising: a plurality of vector register means (12) for storing a plurality of N element vectors, respectively, each of said plurality of vector registers including a plurality of smaller register means (12a) for storing M elements of the corresponding N element vector, where M is less than N; characterized by: a plurality of element processor means (20) each connected to corresponding ones of said smaller register means (12a) for processing the M elements of the vector stored in the smaller register means, each of said smaller register means (12a) and its corresponding element processor means (20) comprising a unit (30), a plurality of the units (30) being connected together in a parallel configuration (40) forming a plurality of units (30, 40) for processing in parallel fashion the N elements of a vector stored in one of said plurality of vector register means (12).
Claim 2
Dependent Claim
146 words
A vector processor, comprising: a plurality of vector register means (12) for storing a plurality of N element vectors, respectively, each of said plurality of vector registers including a plurality of smaller register means (12a) for storing M elements of the corresponding N element vector, where M is less than N; characterized by: a plurality of element processor means (20) each connected to corresponding ones of said smaller register means (12a) for processing the M elements of the vector stored in the smaller register means, each of said smaller register means (12a) and its corresponding element processor means (20) comprising a unit (30), a plurality of the units (30) being connected together in a parallel configuration (40) forming a plurality of units (30, 40) for processing in parallel fashion the N elements of a vector stored in one of said plurality of vector register means (12).
Claim 3
Dependent Claim
54 words
The vector processor of claim 1 further comprising: storage means (52, 54) for storing a plurality of instructions; and control means (50) connected to said storage means and to said plurality of units (30) for controlling the operation of said plurality of units in accordance with an instruction stored in said storage means (54).
Claim 4
Dependent Claim
103 words
The vector processor of claim 2 wherein said plurality of units (30, 40) adds together a plurality of groups of M elements of said N element vector in response to instructions from said control means thereby producing a plurality of subtotals, said plurality of subtotals being stored in a corresponding plurality of units (40), said corresponding plurality of units (40) adds together said plurality of subtotals to produce a final total in response to further instructions from said control means, said final total being stored in a unit (30/0) and being indicative of the sum of the elements of said N element vector.
Claim 5
Dependent Claim
143 words
The vector processor of a previous claim wherein each said element processor means (20) comprises: read means (20a) for reading an element of an N element vector and another element of said N element vector; register means (20b, c) connected to said read means for storing the elements read by said read means; pre - shift means (20f) connected to the register means for shifting the operand associated with said element to align said operand with the operand associated with said another element; operation means (20d, e, g) connected to the pre-shift means for processing the elements thereby producing a set of results; post-shift means (20i) connected to the operation means for receiving said set of results from said operation means and shifting the results a predetermined amount in accordance with the number of similar predetermined type of digits in said results; and
Claim 6
Dependent Claim
30 words
) post operation storage means (20h) for storing the set of results, the set of results being passed to one of the plurality of vector register means for storage therein.
Claim 7
Dependent Claim
30 words
) post operation storage means (20h) for storing the set of results, the set of results being passed to one of the plurality of vector register means for storage therein.
Claim 8
Dependent Claim
14 words
The vector processor of claim 2 or 3 wherein said control means (50) comprises:
Claim 9
Dependent Claim
102 words
5 command means (50a, d, e) connected to said storage means (54) and responsive to said instruction stored in said storage means for transmitting command information to said plurality of units (30), said command information controlling the operation of said plurality of units in accordance with said instruction; address means (50c, h, g) connected to said storage means (52, 54) for transmitting address information to said plurality of units (30) indicative of the addresses of said plurality of units controlled by said command means; and data means (50b, f) connected to said storage means for transmitting data to said plurality of units.
Claim 10
Dependent Claim
102 words
5 command means (50a, d, e) connected to said storage means (54) and responsive to said instruction stored in said storage means for transmitting command information to said plurality of units (30), said command information controlling the operation of said plurality of units in accordance with said instruction; address means (50c, h, g) connected to said storage means (52, 54) for transmitting address information to said plurality of units (30) indicative of the addresses of said plurality of units controlled by said command means; and data means (50b, f) connected to said storage means for transmitting data to said plurality of units.
References Cited (Backward Citations)
No citation records indexed.
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