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Patent EP0136229A2 successfully refreshed from Google Patents.
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EP0136229A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Sense amplifier

Assignee: Fujitsu Ltd
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Filing: 1984-09-14
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Granted: —
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Expires: 2004-09-14
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Abstract

Abstract A sense amplifier of a differential amplifier type having an input selecting function. The sense amplifier comprises a pair of input circuit portions receiving a plurality of pairs of complementary input signals (S,, S 1 ; S 2 , S 2 ...), one of the input circuit portions comprising a plurality of circuit units (Q 41 , Q 51 ; Q 42 , Q 52 ...) each generating the amplified output of one (S,; S 2 ...) of a pair of complementary input signals in response to an address signal (A,; A 2 ; ...) applied thereto, and the other input circuit portion comprising a plurality of circuit units (Q 61 , Q 71 ; Q 62 , Q 72 ; ...) each generating the amplified output of the other one (S,; S2; ...) of the pair of the complementary input signals in response to the address signal (A,; A 2 ; ...) applied thereto. The sense amplifier selects one of a plurality of pairs of complementary input signals, i.e. complementary signals on bit lines or on data buses, in accordance with the address signal and generates an output signal (OUT) corresponding to a selected pair of complementary input signals.

Inventors

  • 👤 Atuo Koshizuka

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-28 20:27
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06; H; H03; H03K; H03K5/00; H03K5/22; H03K5/24; H03K5/2472; H03K5/2481; G11C7/062

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 128 words
A sense amplifier of a differential amplifier type having a pair of input circuit portions receiving a plurality of pairs of complementary input signals, one of said input circuit portions comprising a plurality of circuit units each generating the amplified output of one of a pair of complementary input signals in response to an address signal applied thereto, and the other input circuit portion comprising a plurality of circuit units each generating the amplified output of the other one of said pair of complementary input signals in response to said address signal applied thereto, said sense amplifier selecting one of a plurality of pairs of complementary input signals in accordance with said address signal and generating an output signal corresponding to a selected pair of complementary input signals.
Claim 2
Dependent Claim 128 words
A sense amplifier of a differential amplifier type having a pair of input circuit portions receiving a plurality of pairs of complementary input signals, one of said input circuit portions comprising a plurality of circuit units each generating the amplified output of one of a pair of complementary input signals in response to an address signal applied thereto, and the other input circuit portion comprising a plurality of circuit units each generating the amplified output of the other one of said pair of complementary input signals in response to said address signal applied thereto, said sense amplifier selecting one of a plurality of pairs of complementary input signals in accordance with said address signal and generating an output signal corresponding to a selected pair of complementary input signals.
Claim 3
Dependent Claim 60 words
A sense amplifier according to claim 1, wherein said sense amplifier further comprises a constant current circuit connected between the commonly connected terminals of said input circuit portions and a terminal of a power source, and load circuits each being connected between the output terminal of one of said input circuit portions and the other terminal of said power source.
Claim 4
Dependent Claim 51 words
A sense amplifier according to claim 2, wherein each of said load circuits comprises a MIS transistor, and said constant current circuit comprises a MIS transistor, the gates of the MIS transistors of said load circuits and the gate of the MIS transistor of said constant current circuit being commonly connected.
Claim 5
Dependent Claim 72 words
A sense amplifier according to claim 1 or 2 or 3, wherein each of said circuit units comprises a serial connection of MIS transistors, one of which receives a decoded address signal at the gate thereof and the other receives one of said complementary input signals at the gate thereof, each of said input circuit portions being constituted by a parallel connection of a plurality of said serial connection of MIS transistors.
Claim 6
Dependent Claim 25 words
A sense amplifier according to claim 3, wherein said other MIS transistors of said circuit units are connected to bit lines of a memory device.
Claim 7
Dependent Claim 25 words
A sense amplifier according to claim 3, wherein said other MIS transistors of said circuit units are connected to data buses of a memory device.

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