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EP0136179A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Multiple data path CPU architecture

Assignee: Tandem Computers Inc
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Filing: 1984-09-27
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Granted: —
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Expires: 2004-09-27
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Abstract

Abstract The various functional units which comprise a central pro- cessing unit of a computer are organized so as to enable a main arithmetic logic unit and special function units including an auxilliary arithmetic logic unit to access data registers, literal constants, and data from a memory cache. A general purpose bus closely couples the functional units to the main data paths and allows the CPU sequencer to branch on numerous conditions which may be indicated via test lines. Parity from the functional units is sent a clock cycle later than results in order that the parity path does not affect machine cycle time. The architecture allows unused microcode options to be used to check for correct CPU operation by halting CPU operation on a miscompare of two buses.

Inventors

  • 👤 Robert Whiting Horst
  • 👤 Shannon Joseph Lynch
  • 👤 Cirillo Lino Costantino
  • 👤 John Martin Beirne

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-31 09:48
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885; G06F15/00; G06F15/16; G06F15/163; G06F9/3893; G06F9/3895; G06F9/3897

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 141 words
A pipelined CPU architecture for use in data processing systems including: arithmetic logic means in a first data path for performing arithmetic logic processes on operands; a plurality of selectable special function means in a second data path for processing operands; a plurality of first register means for storing operands to be processed; a plurality of first multiplexer means for choosing selected ones of said operands from said first register means; a plurality of second register means connected to said first multiplexer means for storing said selected ones of said operands; a plurality of second multiplexer means for further choosing among said selected ones of said operands and placing them on said first and second data paths; and bus means for returning results from said arithmetic logic means and said special function means to said first and said second register means.
Claim 2
Dependent Claim 141 words
A pipelined CPU architecture for use in data processing systems including: arithmetic logic means in a first data path for performing arithmetic logic processes on operands; a plurality of selectable special function means in a second data path for processing operands; a plurality of first register means for storing operands to be processed; a plurality of first multiplexer means for choosing selected ones of said operands from said first register means; a plurality of second register means connected to said first multiplexer means for storing said selected ones of said operands; a plurality of second multiplexer means for further choosing among said selected ones of said operands and placing them on said first and second data paths; and bus means for returning results from said arithmetic logic means and said special function means to said first and said second register means.

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