Patent EP0136174B1 successfully refreshed from Google Patents.
EP0136174B1
Expired / Lapsed
EP
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Enhanced alu test hardware
Assignee: Tandem Computers Inc
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Filing: 1984-09-26
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Granted: 1989-12-13
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Expires: 2004-09-26
Abstract
No abstract record available.
Inventors
- 👤 Robert Whiting Horst
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 14:14
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30021; G06F11/00; G06F11/22; G06F11/2205; G06F11/2226; G06F9/30094
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
92 words
Apparatus for performing one or more tests on data presented to the inputs of an arithmetic logic unit in a central processing unit of a data processing system, said arithmetic logic unit having two inputs, characterised by: means directly coupled to both inputs of said arithmetic logic unit for testing whether said data presented on both of said inputs is equal; and by. means directly coupled to both inputs of said arithmetic logic unit for testing whether the logical AND product of said data presented on both of said inputs is zero.
Claim 2
Dependent Claim
92 words
Apparatus for performing one or more tests on data presented to the inputs of an arithmetic logic unit in a central processing unit of a data processing system, said arithmetic logic unit having two inputs, characterised by: means directly coupled to both inputs of said arithmetic logic unit for testing whether said data presented on both of said inputs is equal; and by. means directly coupled to both inputs of said arithmetic logic unit for testing whether the logical AND product of said data presented on both of said inputs is zero.
Claim 3
Dependent Claim
28 words
Apparatus according to claim 1, wherein the tests are performed during the same clock time as the operation of said arithmetic logic unit of said central processing unit.
Claim 4
Dependent Claim
58 words
The apparatus of claim 2, wherein said means for testing whether said data on said two inputs is equal is adapted to generate a first signal such that said first signal assumes a first state if said data on said two inputs are equal and a second state if said data on said two inputs are not equal.
Claim 5
Dependent Claim
56 words
The apparatus of claim 3, wherein said means for testing whether the logical AND product of said data on said two inputs is zero is adapted to generate a second signal such that said second signal assumes a first state if said AND product is zero and a second state if said AND product is non-zero.
Claim 6
Independent Claim
177 words
A method of operating a loop counter routine in a central processing unit of a digital computer, the method comprising the steps of: a) providing a data input, representative of a first desired quantity, to a first input of an arithmetic logic unit, b) providing a data input representing a second desired quantity to a second input of said arithmetic logic unit, c) performing a subtract operation using said arithmetic logic unit during a first clock period; characterised in that the method further comprises the steps of: d) performing an equivalence test on said first and second arithmetic logic unit inputs external to said arithmetic logic unit during said first clock period, and e) terminating said loop counter routine if the result of said equivalence test indicates that first and second arithmetic logic unit inputs are equal and returning the results of said arithmetic logic unit subtract operation to said first input of said arithmetic logic unit if the result of said equivalence test indicates that said first and second arithmetic logic unit inputs are not equal.
Claim 7
Independent Claim
177 words
A method of operating a loop counter routine in a central processing unit of a digital computer, the method comprising the steps of: a) providing a data input, representative of a first desired quantity, to a first input of an arithmetic logic unit, b) providing a data input representing a second desired quantity to a second input of said arithmetic logic unit, c) performing a subtract operation using said arithmetic logic unit during a first clock period; characterised in that the method further comprises the steps of: d) performing an equivalence test on said first and second arithmetic logic unit inputs external to said arithmetic logic unit during said first clock period, and e) terminating said loop counter routine if the result of said equivalence test indicates that first and second arithmetic logic unit inputs are equal and returning the results of said arithmetic logic unit subtract operation to said first input of said arithmetic logic unit if the result of said equivalence test indicates that said first and second arithmetic logic unit inputs are not equal.
References Cited (Backward Citations)
No citation records indexed.
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