Liquid crystal displays checking system and technique

Claim 2

A display driving error detection system comprising: a display having a backplane electrode and plurality of segment electrodes; means for coupling an alternating drive signal to drive said backplane electrode; means for repetitively generating bursts of digital data; drive circuit means responsive to each burst of digital data for coupling a drive signal to each of said plurality of segment electrodes; and means for cyelicly inverting said backplane drive signal and said digital data bursts such that said drive circuit means produces a constant display from each of said segment electrodes when the drive signal of each segment electrode corresponds to the digital data of the digital data burst and an error display of a segment electrode when a drive signal of that electrode differs from the corresponding digital data of said data burst.

Claim 3

A system of claim 1, wherein said drive circuit means comprises a shift register for receiving a plurality of bits of serial data forming said data burst, a latch register coupled to store each bit of said data burst and provide an out-put thereof, and plurality of EXCLUSIVE-OR gates each having a first input coupled to receive a different one of said bits of data and a second input coupled to receive said alternating drive signal and each EXCLUSIVE-OR gate having an output coupled to one of said plurality of segment electrodes to provide the drive signal for that electrode.

Claim 4

The system of claim 1, wherein said error display is a visually blinking display.

Claim 5

The system of claim 2, wherein said means for coupling an alternating drive signal to said backplane comprises an EXCLUSIVE-OR gate having a first input coupled to receive an alternating drive signal, a second input coupled to receive an inverting control signal, and an output coupled to provide a drive signal to said backplane.

Claim 6

The system of claim 4, wherein said means for cyclicly inverting said backplane drive signal and said digital data burst comprises a microprocessor coupled to provide said inverting control signal simultaneous with the inversion of said digital data burst.

Claim 7

In a weighing system having a scale for sensing weight, a means for providing digital data representing that weight, and a liquid crystal display having a backplane electrode and a plurality of segment electrodes responsive to said digital data for displaying said weight, the improvement comprising: drive circuit means for receiving said data representing the weight in data bursts and providing an output drive signal for each segment electrode; means for providing an alternating backplane drive signal to said backplane electrode; and means for cyelicly inverting said backplane drive signal and said digital data bursts such that each segment electrode produces a constant display when a segment electrode drive signal corresponds to the digital data of each burst and each segment electrode provides an error display when the drive signal of that segment electrode differs from the digital data of the burst.

Claim 8

In a weighing system having a scale for sensing weight, a means for providing digital data representing that weight, and a liquid crystal display having a backplane electrode and a plurality of segment electrodes responsive to said digital data for displaying said weight, the improvement comprising: drive circuit means for receiving said data representing the weight in data bursts and providing an output drive signal for each segment electrode; means for providing an alternating backplane drive signal to said backplane electrode; and means for cyelicly inverting said backplane drive signal and said digital data bursts such that each segment electrode produces a constant display when a segment electrode drive signal corresponds to the digital data of each burst and each segment electrode provides an error display when the drive signal of that segment electrode differs from the digital data of the burst.

Claim 9

The system of claim 6, wherein said means for providing an alternating drive signal comprises a square wave generator.

Claim 10

The system of claim 6, wherein said error display is a visually blinking display.

Claim 11

The system of claim 7, wherein said means for inverting comprises a microprocessor coupled to provide a cyclic inverting control signal and simultaneously cyclicly invert the digital data of said data bursts and further including an EXCLUSIVE-OR gate having a first input coupled to receive said inverting signal and a second input coupled to receive a square wave signal from said square wave generator and provide an output as said drive signal to said backplane electrode.

Claim 12

The system of claim 7, wherein said drive circuit means comprises a shift register constructed and arranged to receive serial digital data of each data burst, a latch register coupled to store the digital data received by said shift register and provide outputs of that data and a plurality of EXCLUSIVE-OR gates having a first input coupled to receive a different one of the outputs of said latch register and a second input coupled to receive a square wave signal from said square wave generator and an output coupled to one of said segment electrodes to provide a segment drive signal.

Claim 13

An LCD drive and error detection circuit comprising: a liquid crystal display having a backplane electrode and a plurality of segment electrodes for forming the visual displays; means for serially providing a plurality of digital bits as a data burst; means for generating a clock signal; means for generating a load signal; means for generating a square wave signal; means for generating a control signal; an EXCLUSIVE-OR gate having a first input coupled to receive said control signal, a second input coupled to receive said square wave signal and an output coupled to provide a drive signal to said backplane electrode; drive circuit means for providing a drive signal to each segment electrode in response to said serial digital data burst including a shift register responsive to said clock signal for receiving said plurality of digital bits for each data burst, a latch register responsive to said load signal for storing each digital bit for each data burst and providing and output of that digital bit, and a plurality of EXCLUSIVE-OR gates each having a first input coupled to receive a different one of the outputs of the digital bits of said latch register, a second input coupled to receive said square wave signal and an output coupled to provide a drive signal to one of said segment electrodes; and means coupled to cyclicly invert said control signal and the digital bits of alternate data bursts such that the drive signals to each segment electrode and to the backplane electrode cause a segment electrode to provide a constant visual output when the first input to the EXCLUSIVE-OR gate having an output driving that electrode is the same as its corresponding digital bit in said data burst and cause of segment electrode to provide a visually blinking display when the first input to the EXCLUSIVE-OR gate having an output driving that electrode is different from the corresponding digital bit in said data burst.

Claim 14

An LCD drive and error detection circuit comprising: a liquid crystal display having a backplane electrode and a plurality of segment electrodes for forming the visual displays; means for serially providing a plurality of digital bits as a data burst; means for generating a clock signal; means for generating a load signal; means for generating a square wave signal; means for generating a control signal; an EXCLUSIVE-OR gate having a first input coupled to receive said control signal, a second input coupled to receive said square wave signal and an output coupled to provide a drive signal to said backplane electrode; drive circuit means for providing a drive signal to each segment electrode in response to said serial digital data burst including a shift register responsive to said clock signal for receiving said plurality of digital bits for each data burst, a latch register responsive to said load signal for storing each digital bit for each data burst and providing and output of that digital bit, and a plurality of EXCLUSIVE-OR gates each having a first input coupled to receive a different one of the outputs of the digital bits of said latch register, a second input coupled to receive said square wave signal and an output coupled to provide a drive signal to one of said segment electrodes; and means coupled to cyclicly invert said control signal and the digital bits of alternate data bursts such that the drive signals to each segment electrode and to the backplane electrode cause a segment electrode to provide a constant visual output when the first input to the EXCLUSIVE-OR gate having an output driving that electrode is the same as its corresponding digital bit in said data burst and cause of segment electrode to provide a visually blinking display when the first input to the EXCLUSIVE-OR gate having an output driving that electrode is different from the corresponding digital bit in said data burst.

Claim 15

The system of the claim 11, wherein said means for cyclicly inverting said control signal and data bursts comprises a microprocessor.