EP0134731A1
Expired / Lapsed
EP
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Complementary logic integrated circuit
Assignee: Fujitsu Ltd
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Filing: 1984-07-06
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Granted: —
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Expires: 2004-07-06
Abstract
Abstract A complementary logic circuit which has large power handling capacity, high switching speed and still has low power consumption is formed by a first stage comprising a complementary MIS-FET circuit (Q 1 , Q 2 ), and an output stage comprising complementary bipolar transistors (Q 3 , Q 4 ) or complementary vertical FETs. The output stage (Q 3 , Q 4 ) is provided with pull-up and pull-down elements (l u , I D ), for example in the form of resistors, for which pulling up or pulling down the amplitude of the output signal is set to a value almost equal to that of the power supply voltage. Accordingly, the defect consisting in the lack of amplitude in conventional Bi-MIS circuit to drive C-MIS circuits is eliminated and stable operation of C-MIS logic circuits is secured.
Inventors
- 👤 Osam Ohba
- 👤 Tetsu Tanizawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 07:32
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448; H03K19/0008; H03K19/001; H03K19/01; H03K19/013; H03K19/0136
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
179 words
1 - A complementary logic I C (Integrated Circuit) characterized by : an output stage circuit which comprises a pnp type bipolar transistor (Q 3 ) and a npn type bipolar transistor (Q 4 ), whose collectors are connected to each other and provide an output signal (OUT), and whose emitters are connected respectively to a positive and a negative voltage supply source (V + , V - ); an input stage circuit which comprises a first conductivity type channel MIS-FET (Metal Insulator Semiconductor type Field Effect Transistor) (Q 1 ; Q 6 ) and an opposite conductivity type channel MIS-FET (Q 2 ; Q 5 ), each connected respectively between the base and collector of said pnp and npn type bipolar transistors, and whose gates are connected to each other and receive an input signal (IN); and pull -u p (I U ; Q 9 ) and pull-down (I D ; Q 10 ) elements respectively provided between the base and the voltage supply source of said pnp and npn bipolar transistors (Q 3 , Q 4 ).
Claim 2
Dependent Claim
179 words
1 - A complementary logic I C (Integrated Circuit) characterized by : an output stage circuit which comprises a pnp type bipolar transistor (Q 3 ) and a npn type bipolar transistor (Q 4 ), whose collectors are connected to each other and provide an output signal (OUT), and whose emitters are connected respectively to a positive and a negative voltage supply source (V + , V - ); an input stage circuit which comprises a first conductivity type channel MIS-FET (Metal Insulator Semiconductor type Field Effect Transistor) (Q 1 ; Q 6 ) and an opposite conductivity type channel MIS-FET (Q 2 ; Q 5 ), each connected respectively between the base and collector of said pnp and npn type bipolar transistors, and whose gates are connected to each other and receive an input signal (IN); and pull -u p (I U ; Q 9 ) and pull-down (I D ; Q 10 ) elements respectively provided between the base and the voltage supply source of said pnp and npn bipolar transistors (Q 3 , Q 4 ).
Claim 3
Dependent Claim
149 words
2-A complementary logic IC characterized by : an output stage circuit which comprises a p-channel vertical FET (V-FET) (Q 7 ) and a n-channel V-FET (Q 8 ), whose drains are connected to each other and provide an output signal (OUT), and whose sources are connected respectively to a positive and a negative of voltage supply source; an input stage circuit which comprises a first conductivity type channel MIS-FET (Q 1 ; Q 6 ) and an opposite conductivity type channel MIS-FET (Q 2 ; Q 5 ), each connected respectively between the gate and drain of said p-channel and n-channel V-FETs, and whose gates are connected to each other and receive an input signal (IN); and pull-up and pull-down elements (I U , I D ) respectively provided between the gate and the voltage supply source of said p-channel and n-channel V-FETs (Q 7 . Q 8 ).
Claim 4
Dependent Claim
149 words
2-A complementary logic IC characterized by : an output stage circuit which comprises a p-channel vertical FET (V-FET) (Q 7 ) and a n-channel V-FET (Q 8 ), whose drains are connected to each other and provide an output signal (OUT), and whose sources are connected respectively to a positive and a negative of voltage supply source; an input stage circuit which comprises a first conductivity type channel MIS-FET (Q 1 ; Q 6 ) and an opposite conductivity type channel MIS-FET (Q 2 ; Q 5 ), each connected respectively between the gate and drain of said p-channel and n-channel V-FETs, and whose gates are connected to each other and receive an input signal (IN); and pull-up and pull-down elements (I U , I D ) respectively provided between the gate and the voltage supply source of said p-channel and n-channel V-FETs (Q 7 . Q 8 ).
Claim 5
Dependent Claim
26 words
3 - A complementary logic IC according to Claim 1 or 2, characterized in that said pull-up and pull-down elements are constituted by a resistor (R).
Claim 6
Dependent Claim
30 words
4 - A complementary logic IC according to claim 3, characterized in that said resistor has a resistance value comprised between one and ten times the ON-resistance of said MIS-FETs.
Claim 7
Dependent Claim
37 words
5 - A complementary logic IC according to claim 1 or 2, characterized in that said pull-up and pull-down elements are constituted by a depletion type FET whose gate is connected to the source electrode (Fig. 4.2).
Claim 8
Dependent Claim
45 words
6 - A complementary logic IC according to claim 1 or 2, characterized in that said pull-up and pull-down elements are constituted by a FET whose gate is connected to the drain (Fig. 4.3), said FET having a lower threshold voltage than the bipolar transistors.
Claim 9
Dependent Claim
94 words
7 - A complementary logic IC according to claim 1 or 2, characterized in that said pull-up element is constituted by a n-channel FET (Q 9 ), and said pull-down element is constituted by a p-channel FET (Q 10 ), the gates of said pull-up and pull-down elements (Q 9 . Q 10 ) being connected to the collectors of said pnp and npn bipolar transistors (Q 3 , Q 4 ), or to the drains of said p-channel and n-channel vertical FETs (Q 1 , Q 2 ; Q 6' 0 5 ).
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