Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
91 words
A masterslice semiconductor device / with or without wiring patterns, comprising: a plurality of first basic cell arrays arranged in parallel, each of said first basic cell arrays having a plurality of first basic cells each including at least one transistor; a plurality of second basic cells arrays each arranged between said first basic cell arrays, each of said second basic cell arrays having a plurality of second basic cells each including at least one transistor which has a higher driving capability than the said transistor of a first basic cell.
Claim 2
Dependent Claim
91 words
A masterslice semiconductor device / with or without wiring patterns, comprising: a plurality of first basic cell arrays arranged in parallel, each of said first basic cell arrays having a plurality of first basic cells each including at least one transistor; a plurality of second basic cells arrays each arranged between said first basic cell arrays, each of said second basic cell arrays having a plurality of second basic cells each including at least one transistor which has a higher driving capability than the said transistor of a first basic cell.
Claim 3
Dependent Claim
32 words
A device as claimed in claim 1, wherein each of said first and second basic cells includes a transistor pair having a p-channel MIS (Metal transistor. Insulator Semiconductor) transistor.and a n-channel MIS/
Claim 4
Dependent Claim
53 words
A device as claimed in claim 2, wherein in each basic cell the gates of the p-channel and n-channel transistors in the said transistor pair of the cell extend in line with one another in a direction transverse to the direction in which the arrays extend on a semiconductor substrate of the device.
Claim 5
Dependent Claim
76 words
A device as claimed in claim 3, wherein each basic cell includes a further transistor pair having a p-channel MIS transistor and a n-channel MIS transistor arranged so that the gates of the p-channel transistors of the two transistor pairs in the basic cell concerned extend in parallel with one another and so that the gates of the n-channel transistors of the two transistor pairs in the basic cell concerned extend in parallel with one another.
Claim 6
Dependent Claim
34 words
A device as claimed in claim 2, 3 or 4, wherein in each first basic cell, the p-channel and n-channel transistors of the or each transistor pair have a single common gate. 2 ,
Claim 7
Independent Claim
30 words
A device as claimed in claim/3 or 4, wherein in each second basic cell, the p-channel and n-channel transistors of the or each transistor pair have a single common gate.
Claim 8
Dependent Claim
74 words
A device as claimed in claim 4, or as claimed in claim 5 or 6, when read as appended to claim 4, wherein, in each first basic cell, sources or drains of the two p- channel transistors of the said transistor pairs of the cell concerned occupy a single p-type region and sources or drains of the two n-channel transistors of the said transistor pairs of the cell concerned occupy a single n-type region.
Claim 9
Dependent Claim
79 words
A device as claimed in claim 4, or as claimed in claim 5 or 6 when read as appended to claim 4, or as claimed in claim 7, wherein, in each second basic cell, sources or drains of the two p-channel transistors of the said transistor pairs of the cell concerned occupy a single p-type region and sources or drains of the two n-channel transistors of the said transistor pairs of the cell concerned occupy a single n-type region.
Claim 10
Dependent Claim
55 words
A masterslice semiconductor device as claimed in any preceding claim, with wiring patterns, having wirings disposed on said second basic cells for interconnecting said first basic cells, wherein at least one of the second basic cells in a second basic cell array is utilized to constitute a circuit in conjunction with the first basic cells.