Apparatus for testing integrated circuits

Claim 2

Apparatus for testing integrated circuits comprising: first planar support means having a first opening therethrough; a plurality of first connector means affixed to said first support means and extending therethrough wherein said first connector means are arranged peripherally about said first opening; second planar support means spaced apart from and substantially parallel to said first support means, said second suppport means having a second opening therethrough concentric with said first opening; a plurality of second connector means affixed to said second support means and arranged peripherally about said second opening for connection to said first connector means; a plurality of probe support means affixed to one surface of said second support means at the periphery of said second opening and extending radially inward therefrom; and a plurality of probe means each affixed to one of said plurality of probe support means and having one end connected to one of said plurality of second connector means, the other end of each said probe means extending through said second opening to form a predetermined probe means configuration.

Claim 3

The apparatus of Claim 1, further comprising: means affixed to said first support means for selectively coupling first test signals to selected first connector means.

Claim 4

The apparatus of Claim 2, further comprising: means for successively positioning each integrated circuit die on a semiconductor wafer so that the inputs and outputs thereof are in contact with said plurality of probe means.

Claim 5

The apparatus of Claim 3 wherein said positioning means includes means for controlling the temperature of said semiconductor wafer.

Claim 6

The apparatus of Claim 4, further comprising: third planar support means having a third opening therethrough concentric with said first and second openings, said third support means spaced apart from the surface of said first support means opposite said second support means; a plurality of third connector means affixed to said third support means and arranged peripherally about said third opening for connection to said plurality of first connector means; and means for selectively coupling second test signals to selected third connector means.

Claim 7

The apparatus of Claim 5 wherein said first test signals comprise steady-state logic signals and said second test signals comprise high speed dynamic logic signals.

Claim 8

The apparatus of Claim 6 wherein said first and third planar support means are affixed to a rigid mounting means extending substantially about their entire peripheries.

Claim 9

Apparatus for testing integrated circuits comprising: first planar support means having a centrally located first opening therethrough and including a plurality of first connector means affixed to the upper and lower surfaces thereof, said first connector means located peripherally about said first opening; second planar support means having an upper surface spaced apart from the lower surface of said first support means and having a centrally located second opening therethrough concentric with said first opening, said second planar support means including a plurality of second connector means affixed to the upper surface thereof and located peripherally about said second opening wherein said second connector means are detachably coupled to said first connector means affixed to the lower surface of said first support means; a plurality of probe support means affixed to the upper surface of said second support means at the periphery of said second opening and extending radially inward therefrom; a plurality of probe means each affixed to one of said plurality of probe support means and having one end connected to one of said plurality of second connector means, the other end of each said probe means extending through said second opening below the lower surface of said second support means to form a predetermined probe means configuration; and means for successively positioning each integrated circuit die on a semiconductor wafer so that the inputs and outputs thereof are in contact with said plurality of probe means.

Claim 10

Apparatus for testing integrated circuits comprising: first planar support means having a centrally located first opening therethrough and including a plurality of first connector means affixed to the upper and lower surfaces thereof, said first connector means located peripherally about said first opening; second planar support means having an upper surface spaced apart from the lower surface of said first support means and having a centrally located second opening therethrough concentric with said first opening, said second planar support means including a plurality of second connector means affixed to the upper surface thereof and located peripherally about said second opening wherein said second connector means are detachably coupled to said first connector means affixed to the lower surface of said first support means; a plurality of probe support means affixed to the upper surface of said second support means at the periphery of said second opening and extending radially inward therefrom; a plurality of probe means each affixed to one of said plurality of probe support means and having one end connected to one of said plurality of second connector means, the other end of each said probe means extending through said second opening below the lower surface of said second support means to form a predetermined probe means configuration; and means for successively positioning each integrated circuit die on a semiconductor wafer so that the inputs and outputs thereof are in contact with said plurality of probe means.

Claim 11

The apparatus of Claim 8 wherein said positioning means includes means for controlling the temperature of said semiconductor wafer.

Claim 12

The apparatus of Claim 9, further comprising: means affixed to said first support means for selectively coupling first test signals to selected first connector means.

Claim 13

The apparatus of Claim 10, further comprising: third planar support means having a centrally located third opening therethrough concentric with said first and second openings, said third support means spaced apart from the upper surface of said first support means and including a plurality of third connector means affixed to the upper and lower surfaces thereof, wherein said third connector means are located peripherally about said third opening, said lower surface third connector means being connected to said upper surface second connector means.

Claim 14

The apparatus of Claim 11, further comprising: means affixed to said third support means for selectively coupling second test signals to selected third connector means.

Claim 15

The apparatus of Claim 12 wherein said first test signals comprise steady-state logic signals and said second test signals comprise high speed dynamic logic signals.

Claim 16

The apparatus of Claim 13 wherein said second test signal coupling means includes isolation amplifier means coupled to each of said plurality of third connector means.

Claim 17

The apparatus of Claim 14 wherein said second support means, said probe support means, and said probe means are formed of materials having a low temperature coefficient of thermal expansion.

Claim 18

The apparatus of Claim 15 wherein each of said second support means is formed of a polyimide resin.

Claim 19

The apparatus of Claim 16 wherein said probe support means is formed of ceramic.

Claim 20

The apparatus of Claim 17 wherein said probe means are formed of tungsten or a tungsten alloy.