Semiconductor memory device

Claim 1

A semiconductor memory device comprising: a plurality of word lines; a plurality of bit line pairs; a plurality of memory cells located at each cross point of said word lines and said bit line pairs, each of which memory cells is composed of a pair of bipolar transistors in the form of a flip-flop; a plurality of word drivers connected to respective said word lines and activated when a corresponding word line is to be selected by a corresponding word selection signal given by a word decoder; and a plurality of bit drivers for each said bit line pair, operative to specify a desired one of said memory cells, characterized in that each of said word lines is divided to form, along the word line, a plurality of word line segments, each of which, apart from a first word line segment activated by the word driver directly receiving a corresponding said word selection signal, is provided with an individual private word driver and is activated thereby when the corresponding word selection signal is given to supply current individually to said memory cells pertaining thereto, a first private word driver being operable to be activated in response to a word line signal appearing at the first word line segment, and secondand following private word drivers being operableto be activated in response to word line signals appearing at preceding word line segments, respectively.