Abstract An electrical circuit is described that requires a reduced number of data bits for character-address and video-mode information by using a predetermined bit combination of the video-mode information as part of the character-address information. Character-address and video-mode information is outputted from a random access memory RAM (24) to a character read only memory ROM (26) and a video-mode detection circuit (28) that produces outputs to enable video-mode circuits in the video control circuitry. One output of the video-mode detection circuit is coupled to an address input of the character ROM (26) that has characters divided into two character sets. A predetermined bit combination of the video-mode information produces an output from the video-mode detection circuit that selects one of the character sets while the other bit combinations produce an output from the detection circuit that selects the other character set. In this way, character-address and video-mode information having n data bits can produce character and video-mode outputs that normally require N + data bits.
Inventors
👤 Daniel C. Olin
👤 Russell Y. Anderson
👤 Steven C. Denbeste
Bibliographic Details
Application Number—
JurisdictionEP
Data Sourcegoogle_patents
Last Synchronized2026-10-29 14:27
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/22; G09G5/222
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
86 words
An electrical circuit,characterized by means (26) for storing a plurality of electrical patterns, representative of character information, said storage means (26) being coupled to receive a first portion of a coded electrical signal and at least one control signal to produce an output electrical signal corresponding to said electrical patterns; means (28) for detecting a second portion of said coded electrical signal to produce said control signal coupled to said storage means (26) and to produce additional control signals representative of attributes of said electrical patterns.
Claim 2
Dependent Claim
86 words
An electrical circuit,characterized by means (26) for storing a plurality of electrical patterns, representative of character information, said storage means (26) being coupled to receive a first portion of a coded electrical signal and at least one control signal to produce an output electrical signal corresponding to said electrical patterns; means (28) for detecting a second portion of said coded electrical signal to produce said control signal coupled to said storage means (26) and to produce additional control signals representative of attributes of said electrical patterns.
Claim 3
Dependent Claim
34 words
The electrical circuit of claim l,characterized in that said storage means (26) is a read only memory (ROM) having electrical patterns addressable by said first part of coded electrical signal and said control signal.
Claim 4
Dependent Claim
58 words
The electrical circuit of claim 1 or 2, characterized in that said detection means comprises a first and a second NAND gate (30,32) and a data latch (34) such that said second portion of coded electrical signal is coupled to the inputs of said first NAND gate (30) and to the data inputs of said data latch (34).
Claim 5
Dependent Claim
49 words
The detection means of claim 3, characterized in that the output of said first NAND gate (30) is said control signal coupled to said storage means (26) and the outputs (Q1,Q2) of said data latch (34) are the said additional control signals representative of attributes of said electrical patterns.
References Cited (Backward Citations)
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