Method for fabricating DEIS structure between two polysilicon gate electrodes and memories resulting therefrom

Claim 1

Method for fabricating a DEIS structure between two layers of polysilicon in an array of devices embedded in an integrated circuit substrate characterized in that it comprises the following steps: (a) fabricating a silicon substrate with at least one thin oxide region surrounded by thick oxide region; (b) depositing a first polysilicon gate interconnect layer on the substrate; (c) depositing on said first polysilicon gate interconnect layer, a composite DEIS structure of three layers : a first layer of silicon rich oxide, a layer of silicon dioxide, a second layer of silicon rich oxide; a second layer of polysilicon and a layer of non-oxidizing material with the layers being deposited in the order of recitation; (d) patterning a first photoresist mask on the layer of non-oxidizing material with said photoresist defining a profile for the DEIS structure; (e) etching the exposed areas through the said non-oxidizing material, through the said second layer of polysilicon; (f) etching the exposed DEIS areas; (g) stripping the first photoresist mask; (h) patterning a second photoresist mask on the layer of the non-oxidizing material; said second photoresist mask being operable to define at least one polysilicon floating gate electrode and polysilicon interconnections; (i) etching the exposed polysilicon areas; (j) stripping the second photoresist mask; (k) thermally oxidizing the structure for isolating at least one floating gate; (1) removing the layer of non-oxidizing material; (m) depositing a third layer of polysilicon on the second layer of polysilicon previously laid down in step (b) above; and (n) forming electrical interconnections and gate electrodes in said third layer of polysilicon.