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EP0123563A2
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Converting digital signals
Assignee: Sony Corp
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Filing: 1984-04-26
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Granted: —
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Expires: 2004-04-26
Abstract
Abstract A converted digital signal is provided in NRZI code with a dc component of zero and with a maximum number of four bits between level transitions in the signal. The base digital signal is divided into 8-bit base words, each of which is then converted into a 10-bit converted word to form a converted digital signal suitable for recording. Of the 1024 (2'°) possible 10-bit combinations, there are 193 that begin with no more than two digital zeros, end with no more than one digital zero, have no more than three consecutive digital zeros anywhere else and have a dc component of zero when NRZI-coded. Each of these 193 primary 10-bit combinations is used to represent one 8-bit base word. Each remaining 63 of the total 256 (2 8 ) base words is converted into a secondary 10-bit combination which has a "convention" dc component of +2 or -2, defined as the dc component when the combination is NRZI-coded and the preceding combination ends at the signal's lower level, but which otherwise meets the description of the 193 primary 10-bit combinations. Beginning with the first bit of one secondary combination, the number of level transitions in the converted digital signal, when NRZI- coded, are detected up to the end of the 10-bit combination immediately preceding the next secondary combination. Depending on the number of level changes, the first bit of the next secondary combination is provided to give that secondary combination a convention dc component which eliminates the actual dc component in the portion of the signal containing the pair of secondary combinations.
Inventors
- 👤 Shinichi C/O Patent Division Fukuda
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-10 01:36
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1423; G11B20/1426; G11B5/00; G11B5/02; G11B5/09
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
189 words
A method of providing a digital signal having at least two signal levels, a dc component substantially equal to zero and a predetermined maximum time between level transitions, the method comprising: dividing a base digital signal into a series of base words each with n bits of data; and converting said base digital signal into a converted digital signal by matching a converted word with each said base word, each said converted word having m bits of data, wherein m is greater than n and said converted digital signal has a predetermined maximum number of consecutive digital zeros; characterised by: said converted words including a plurality of primary combinations of m bits having a dc component substantially equal to zero when NRZI-coded and a plurality of secondary combinations of m bits having a dc component with an absolute value of two when NRZI-coded; supplying said secondary combinations with dc components when NRZI-coded so that a portion of said converted digital signal including a pair of said secondary combinations has a dc component substantially equal to zero when NRZI-coded; and generating said converted digital signal as an NRZI-coded digital signal.
Claim 2
Independent Claim
189 words
A method of providing a digital signal having at least two signal levels, a dc component substantially equal to zero and a predetermined maximum time between level transitions, the method comprising: dividing a base digital signal into a series of base words each with n bits of data; and converting said base digital signal into a converted digital signal by matching a converted word with each said base word, each said converted word having m bits of data, wherein m is greater than n and said converted digital signal has a predetermined maximum number of consecutive digital zeros; characterised by: said converted words including a plurality of primary combinations of m bits having a dc component substantially equal to zero when NRZI-coded and a plurality of secondary combinations of m bits having a dc component with an absolute value of two when NRZI-coded; supplying said secondary combinations with dc components when NRZI-coded so that a portion of said converted digital signal including a pair of said secondary combinations has a dc component substantially equal to zero when NRZI-coded; and generating said converted digital signal as an NRZI-coded digital signal.
Claim 3
Independent Claim
67 words
A method according to claim I wherein said base words are individually stored and converted into said converted words, each said converted word is stored and said dc component is determined while said converted word is stored, said converted words are read from storage to form said converted digital signal and said NRZI-coded digital signal is generated from said converted words after the reading thereof from storage.
Claim 4
Dependent Claim
26 words
A method according to claim 1 wherein n is eight, m is ten, and said converted digital signal has a maximum of three consecutive digital zeros.
Claim 5
Dependent Claim
98 words
A method according to claim 3 wherein: said digital signals are bi-level signals; said primary combinations begin with a maximum of two digital zeros, end with a maximum of one digital zero, and have a maximum of three consecutive digital zeros anywhere therein; and said secondary combinations have convention dc components, defined as the dc component when the preceding combination ends at the lower signal level when NRZI-coded, of +2 and -2, with a maximum of two digital zeros, end with a maximum of one digital zero, and have a maximum of three consecutive digital zeros anywhere therein.
Claim 6
Dependent Claim
30 words
A method according to claim 4 wherein each said secondary combination when NRZI-coded has an actual dc component different from the actual dc component of the preceding said secondary combination.
Claim 7
Dependent Claim
112 words
A method according to claim 5 wherein each said secondary combination is chosen from two complementary 10-bit combinations differing only in the first bit of data thereof, the method further comprising: detecting the level transitions in a portion of said converted signal, when NRZI-coded, beginning with the first bit of data of each said secondary combination; and selecting the next secondary combination from said complementary secondary combinations so that said secondary combination has the same convention dc component as said next-preceding secondary combination when said number of detected level transitions is odd and a different convention dc component from said next-preceding secondary combination when said number of detected level transitions is even.
Claim 8
Dependent Claim
103 words
A method according to claim 4 wherein said secondary combinations are chosen from the 10-bit combinations beginning with a digital zero, the method further comprising: counting the level transitions in said converted digital signal, when NRZI-coded, beginning with the first bit of data of a secondary combination; and inverting the first bit of data in the next secondary combination when said number of counted level transitions is even and said convention dc components of said two secondary combinations are the same and when said number of counted level transitions is odd and said convention dc components of said two secondary combinations are different.
Claim 9
Dependent Claim
93 words
B. A method according to claim 3 wherein said digital components, defined as the dc component of a combination when the preceding combination ends at the lower signal level when NRZI-coded, of said secondary combinations are substantially equal, the method further comprising: counting the level transitions in said converted digital signal, when NRZI-coded, beginning with the first bit of data of a secondary combination; and inverting the first bit of data in the next said secondary combination if the number of said counted level transitions prior to said next secondary combination is even.
Claim 10
Dependent Claim
21 words
A method according to claim 7 wherein the first bit of data in each said secondary combination is a digital zero.
Claim 11
Dependent Claim
79 words
A method according to claim 8 wherein: said primary combinations begin with a maximum of two digital zeros, end with a maximum of one digital zero, and have a maximum of three consecutive digital zeros anywhere therein; and said secondary combinations when NRZI-coded have a convention dc component substantially equal to -2, begin with a maximum of two digital zeros, end with a maximum of one digital zero, and have a maximum of three consecutive digital zeros anywhere therein.
Claim 12
Dependent Claim
119 words
A method according to claim 3 wherein said primary combinations consist of the 193 10-bit combinations having a dc component substantially equal to zero when NRZI-coded, begin with a maximum of two digital zeros, end with a maximum of one digital zero and have a maximum of three consecutive digital zeros anywhere therein, and said secondary combinations are chosen from the remaining 10-bit combinations having a dc component with an absolute value of two, beginning with a maximum of two digital zeros, ending with a maximum of one digital zero and having a maximum of three consecutive digital zeros therein, each said secondary combination ending with a combination of nine bits of data unique to that said secondary combination.
Claim 13
Dependent Claim
100 words
A method of restoring said converted digital signal generated in accordance with the method of claim 1 comprising the steps of: demodulating said NRZI-coded digital signal into a reconstituted digital signal; dividing said reconstituted digital signal into a series of reconstituted words each with m bits of data and respectively corresponding to one of said m-bit converted words; converting each said reconstituted word into a restored word with n bits, said restored word corresponding to the n-bit base word that was converted into said one converted word; and supplying said reconverted digital signal as a series of said reconverted words.
Claim 14
Dependent Claim
117 words
A method of restoring said converted digital signal generated in accordance with the method of claim 11 comprising the steps of: demodulating said NRZI-coded digital signal into a reconstituted digital signal; dividing said reconstituted digital signal into a series of reconstituted words each with ten bits of data and respectively corresponding to one of said 10-bit converted words; converting each said reconstituted word into a restored word with eight bits, said restored word corresponding to the 8-bit base word that was converted into said one converted word, by providing said reconstituted words corresponding to said secondary combinations without regard to the first bit thereof; and supplying said reconverted digital signal as a series of said reconverted words.
Claim 15
Dependent Claim
224 words
Converting apparatus for providing a digital signal having at least two signal levels, a dc component substantially equal to zero and a predetermined maximum time between level changes, the apparatus comprising: dividing means (2) for dividing a base digital signal into a series of base words each with n bits of data; and programmed memory means (3) for converting each said base word into a matching converted word, each with m bits of data, wherein m is greater than n and said converted words, when arranged serially, form a converted signal with a predetermined maximum number of consecutive digital zeros; characterised by: said memory means (3) being such that said converted words include a plurality of primary combinations of m bits having a dc component substantially equal to zero when NRZI-coded and a plurality of secondary combinations having a dc component with an absolute value of two when NRZI-coded, and such as to provide said secondary combinations with dc components when NRZI-coded so that a portion of said converted signal including a pair of said secondary combinations has a dc component substantially equal to zero when NRZI-coded; combining means (4) for accepting said converted words from said memory means (3) and supplying said converted words in a series to form said converted signal; and modulating means (6) for supplying said converted signal in NRZI-code.
Claim 16
Dependent Claim
224 words
Converting apparatus for providing a digital signal having at least two signal levels, a dc component substantially equal to zero and a predetermined maximum time between level changes, the apparatus comprising: dividing means (2) for dividing a base digital signal into a series of base words each with n bits of data; and programmed memory means (3) for converting each said base word into a matching converted word, each with m bits of data, wherein m is greater than n and said converted words, when arranged serially, form a converted signal with a predetermined maximum number of consecutive digital zeros; characterised by: said memory means (3) being such that said converted words include a plurality of primary combinations of m bits having a dc component substantially equal to zero when NRZI-coded and a plurality of secondary combinations having a dc component with an absolute value of two when NRZI-coded, and such as to provide said secondary combinations with dc components when NRZI-coded so that a portion of said converted signal including a pair of said secondary combinations has a dc component substantially equal to zero when NRZI-coded; combining means (4) for accepting said converted words from said memory means (3) and supplying said converted words in a series to form said converted signal; and modulating means (6) for supplying said converted signal in NRZI-code.
Claim 17
Dependent Claim
82 words
Converting apparatus according to claim 14 wherein: said dividing means (2) includes a series-to-parallel shift register (2) for simultaneously supplying eight bits of the base digital signal to said memory means (3); said combining means (4) includes a parallel-to-series shift register (4) for accepting ten bits of data comprising a converted word and supplying said bits one-by-one as said converted digital signal; and said modulating means (6) includes a JK flip-flop circuit (6) for accepting said bits from said parallel-to-series register (4).
Claim 18
Dependent Claim
126 words
Converting apparatus according to claim 14 wherein said memory means (3) detects the number of level transitions in each said converted word and supplies a count signal in response to said detection for indicating whether said number is even or odd and includes logic means (8) for supplying a control signal in response to said count signal to indicate whether the total number of level transitions in said portion of said converted digital signal, when NRZI-coded, beginning with the first bit of data thereof is odd or even, and said memory means (3) provides the next said secondary combination of said pair with a dc component different from the dc component of the preceding said secondary combination of said pair in response to said control signal.
Claim 19
Dependent Claim
89 words
Converting apparatus according to claim 16 wherein: said digital signals are bi-level signals; said secondary combinations have substantially equal convention dc components, defined as the dc component of a combination when the preceding combination ends at the lower signal level when NRZI-coded, and begin with a digital zero; and said memory means (3) inverts the first bit of data in the next said secondary combination of said pair when said control signal indicates that said number of level transitions from the beginning of said preceding secondary combination is even.
Claim 20
Dependent Claim
216 words
Converting apparatus according to claim 16 wherein said first bit of data of each said secondary combination is a digital zero prior to inversion and said logic means (8) includes: a detector circuit (18) for accepting said base words and supplying a detection signal and a reset signal as digital ones when said corresponding converted word is a secondary combination and as digital zeros when said corresponding converted word is a primary combination, wherein said detector circuit (18) provides said reset signal as a digital zero for every other said secondary combination; a counter (28) for detecting the number of level changes in said converted digital signal when NRZI-coded and supplying said count signal as a digital zero when said number is even, said counter (28) including a reset terminal for accepting said reset signal and resetting said counter (28) to zero when said reset signal is a digital one; an AND circuit (38) for accepting said detection signal and said count signal and supplying said control signal in response thereto; and an OR circuit (48) for accepting said control signal and the first bit of data of said converted word and supplying as the output of said OR circuit (38) the first bit of data of said converted word to said parallel-to-series shift register (4).
Claim 21
Dependent Claim
28 words
Converting apparatus according to claim 18 wherein each said secondary combination has a convention dc component of -2 prior to inversion of the first bit of data thereof.
Claim 22
Dependent Claim
70 words
Converting apparatus according to claim 16 wherein: said digital signals are bi-level signals; said secondary combinations have convention dc components, defined as the dc component of a combination when the preceding combination end at the lower signal level when NRZI-coded, of +2 and -2; and said memory means (3) supplies each said secondary combination with an actual dc component different from the actual dc component of said previous secondary combination.
Claim 23
Dependent Claim
130 words
Converting apparatus according to claim 20 wherein: said dividing means (2) comprises a master clock (9') for providing a master clocking signal; said memory means (3') is programmed to select said secondary combinations from two complementary 10-bit combinations differing only in the first bit of data thereof in response to said control signal and to read said converted words and corresponding latch signal, which latch signal is generated from said count signal and said control signal by said memory means (3'), in response to said master clocking signal; and said logic means includes a latch means (8') for accepting said latch signal supplied for each said converted word and supplying said latch signal as the control signal for the next-following said converted word in response to said master clocking signal.
Claim 24
Dependent Claim
186 words
Converting apparatus according to claim 21 wherein: said memory means (3') generates a parity bit as said count signal for each converted word, said parity bit being a digital one if the number of level transitions in said converted word is odd and a digital zero if the number of level transitions in said converted word is even; said control signal is a digital zero or digital one and said memory means (3') supplies said secondary combinations with convention dc components of +2 when said control signal is a digital zero and with convention dc components of -2 when said control signal is a digital one; and said memory means (3') generates said latch signal for primary combinations as a digital zero if said control signal and said parity bit therefor are the same and as a digital one if said control signal and said parity bit therefor are different, and for secondary combinations as a digital one if said control signal and said parity bit therefor are the same and as a digital zero if said control signal and said parity bit therefor are different.
Claim 25
Dependent Claim
40 words
Converting apparatus according to claim 15 wherein said dividing means (2) includes a master clock (9) for supplying a master clocking signal to control reading of said converted words from said memory means (3) into said parallel-to-series shift register (4).
Claim 26
Dependent Claim
51 words
Apparatus according to claim 23 wherein m is ten and n is eight and said parallel-to-series shift register (4) and said JK flip-flop (6) are controlled by a reading clock (5) that generates a reading clocking signal having a clock rate 5/4 of the clock rate of said master clocking signal.
Claim 27
Dependent Claim
16 words
Apparatus according to claim 15 wherein said programmed memory means (3) is a read-only memory (3).
References Cited (Backward Citations)
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