Semiconductor memory device having a floating gate

Claim 2

A semiconductor memory device comprising: a semiconductor substrate of one conductivity type (11, 21, 31); first and second semiconductor regions of the opposite conductivity type (12 and 13, 22 and 23, 33 and 34) formed in the surface area of said semiconductor substrate (11, 21, 31); a floating gate (FG2, FG3, FG4) insulatively formed over a first channel region (11A, 21B, 31B) between said first and second semiconductor regions (12 and 13, 22 and 23, 33 and 34); and a first control gate (CG2, 25, CG4-1 and CG4-2) disposed to face said floating gate (FG2, FG3, FG4), characterized in that the effective area of portion of said first control gate (CG2, 25, CG4-1 and CG4-2) which faces said floating gate (FG2, FG3, FG4) is set to be smaller than the effective area of portion of said floating gate (FG2, FG3, FG4) which faces the active region including said first and second semiconductor regions .(12 and 13, 22 and 23, 33 and 34) and said first channel region (11A, 21B, 31B).

Claim 3

A semiconductor memory device according to claim 1, characterized by further comprising a third semiconductor region (14, 24, 35) of the opposite conductivity type formed in the surface area of said substrate (11, 21, 31), and a selection gate insulatively formed over a second channel region between said second and third semiconductor regions (13 and 14, 23 and 24, 34 and 35).

Claim 4

A semiconductor memory device according to claim 1 or 2, characterized in that said second semiconductor region (13, 34) is formed to extend into an area under said floating gate (FG2, FG4) to make the effective area of portion of said second semiconductor region (13, 34) which faces said floating gate (F G 2, F G4) larger than the effective area of portion of said first control gate (CG2, CG4-1 and CG4-2) which faces said floating gate (FG2, FG4).

Claim 5

A semiconductor memory device according to claim 1, 2 or 3, characterized by further comprising a fourth semiconductor region (32) of the opposite conductivity type formed in the surface area of said substrate (31), and a second control gate (CG3) electrically coupled with said first control gate (CG4-1 and CG4-2) and insulatively formed over a channel region (31A) between said first and second semiconductor regions (32 and 33).

Claim 6

A semiconductor memory device according to claim 4,.characterized in that said first control gate includes first and second control gate sections (CG4-1 and CG4-2) which are formed in parallel to each other and to face respective end portions of said floating gate.(FG4).

Claim 7

A semiconductor memory device according to claim 1 or 2, characterized in that said first control gate is formed of a semiconductor region (25) of the opposite conductivity type formed in the surface area of said substrate (21).

Claim 8

A semiconductor memory device according to. claim.6, characterized in that said floating gate (FG3) is formed to have first, second and third portions which respectively face said second semiconductor region (23), first channel region (21B) and first control gate (25); the effective area of said first portion being larger than the sum of the effective areas of said second and third portions.

Claim 9

A semiconductor memory device according to claim 1 or 2, characterized in that said second semiconductor region (13, 34) is formed to extend into an area under said floating gate (FG2, FG4) to make the effective area of portion of said second semiconductor region (13, 34) which faces said floating gate (FG2, FG4) larger than the sum of the effective areas of portions of said first semiconductor region (12, 33) and first channel region (11A, 31B) which face said floating gate (FG2, FG4).

Claim 10

A semiconductor memory device comprising a semiconductor-substrate of one conductivity type (31); first to third semiconductor regions of an opposite conductivity type (32, 33, 35) formed in the surface area of said substrate (31); a first control gate (CG3) insulatively formed over a first channel region (31A) between said first and second semiconductor regions (32, 33); a floating gate (FG4) insulatively formed over a second channel region (31B) which is formed in contact with said second semiconductor region (33); a second control gate (CG4-1, CG4-2) insulatively formed over said floating gate (FG4); a third control gate (SG5) insulatively formed over a third channel region (31D) which is formed between and in contact with said second channel region (31B) and third semiconductor region (35), wherein the area of said second control gate (CG4-1, CG4-2) which faces said floating gate (FG4) is made smaller than the area of an active region which includes said second semiconductor region (33) and second and third channel regions (31B, 31D) and which faces said floating gate (FG4).

Claim 11

A semiconductor memory device comprising a semiconductor-substrate of one conductivity type (31); first to third semiconductor regions of an opposite conductivity type (32, 33, 35) formed in the surface area of said substrate (31); a first control gate (CG3) insulatively formed over a first channel region (31A) between said first and second semiconductor regions (32, 33); a floating gate (FG4) insulatively formed over a second channel region (31B) which is formed in contact with said second semiconductor region (33); a second control gate (CG4-1, CG4-2) insulatively formed over said floating gate (FG4); a third control gate (SG5) insulatively formed over a third channel region (31D) which is formed between and in contact with said second channel region (31B) and third semiconductor region (35), wherein the area of said second control gate (CG4-1, CG4-2) which faces said floating gate (FG4) is made smaller than the area of an active region which includes said second semiconductor region (33) and second and third channel regions (31B, 31D) and which faces said floating gate (FG4).