Patent EP0120525A2 successfully refreshed from Google Patents.
EP0120525A2
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EP
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Memory pack addressing system
Assignee: Tektronix Inc
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Filing: 1984-02-27
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Granted: —
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Expires: 2004-02-27
Abstract
Abstract Disclosed herein is a system for addressing a memory pack having a plurality of memory chips such as RAMs or ROMs. Each memory chip receives address signals and a chip enable signal. A chip selector generates the chip enable signal in response to a feedback signal from the memory pack provided in response to the memory address lines. Since each memory pack excludes the chip selector circuitry, the memory packs can be made smaller in size. The memory packs are in effect self-configuring since they control the feedback of the address signals to the chip selector which generates the chip enable signals. Many types and capacities of memory packs can be mixed in the system since the pack determines the memory address space in which it resides.
Inventors
- 👤 Russell Y. Anderson
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 10:57
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G11; G11C; G11C8/00; G11C8/12
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
96 words
A system for selectively addressing one of a plurality of chips in a plurality of memory packs, said system comprising: a processor means for providing a plurality of memory address signals along a signal bus; decoder means for providing memory selection signals in response to a feedback signal; a memory pack means having a plurality of memory chips coupled to said decoder means for providing said feedback signal in response to preselected ones of said memory address dress signals and for enabling a memory chip selected by said memory address signals and said memory selection signals.
Claim 2
Independent Claim
96 words
A system for selectively addressing one of a plurality of chips in a plurality of memory packs, said system comprising: a processor means for providing a plurality of memory address signals along a signal bus; decoder means for providing memory selection signals in response to a feedback signal; a memory pack means having a plurality of memory chips coupled to said decoder means for providing said feedback signal in response to preselected ones of said memory address dress signals and for enabling a memory chip selected by said memory address signals and said memory selection signals.
Claim 3
Dependent Claim
34 words
The system as in claim 1 wherein said memory pack means is coupled to said processor means via a connector which couples the memory pack means to said processor means and said decoder means.
Claim 4
Dependent Claim
31 words
A system according to claim 1, wherein the memory pack means provides said feedback signal in response to the number and memory capacity of said memory chips within said memory pack.
Claim 5
Dependent Claim
16 words
A memory pack addressing system according to claim 3, wherein said chip selector is a decoder.
Claim 6
Dependent Claim
82 words
A system according to claim 1 wherein said processor provides bank addressing signals and wherein said memory pack includes a plurality of memory banks, said memory banks being selectively enabled by a bank selection signal, said memory pack further comprising means to provide a bank feedback signal in response to said bank address signals, and wherein said system further comprises: a bank selector means coupled to said processor means for providing said bank selection signal in response to said bank feedback signal.
Claim 7
Dependent Claim
16 words
A memory pack addressing system according to claim 5, wherein said bank selector is a decoder.
Claim 8
Dependent Claim
32 words
A memory pack addressing system according to claim 5, wherein said bank selector means receives a bank selection signal from said processor means via a signal path provided in said memory pack.
Claim 9
Dependent Claim
17 words
A memory pack addressing system according to claim 1, wherein said memory chips are random access memories.
Claim 10
Dependent Claim
17 words
A memory pack addressing system according to claim 1, wherein said memory chips are read only memories.
References Cited (Backward Citations)
No citation records indexed.
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