EP0120424A2 — Parallel comparison type analog to digital conver…

Claim 1

Independent Claim 225 words

A parallel comparison analog to digital converter of the type having; a voltage dividing circuit for generating a plurality of ordered comparison voltages; an equal plurality of ordered comparison circuits for comparing said plurality of voltages, respectively, with a common analog input voltage to be digitally converted; a position detecting circuit responsive to the outputs of said plurality of comparison circuits for developing a digital output dependent upon the order of the crossover between those comparison circuits which receive a lower comparison voltage than said common analog input voltage and those comparison circuits which receive a higher comparison voltage than said common analog input voltage; said comparison circuits being of the type which' produce a first binary level output when said analog input voltage is sufficiently above said comparison voltage, a second binary level output when said analog input voltage is sufficiently below said comparison voltage, and an intermediate level output when said analog input is neither sufficiently above nor sufficiently below said comparison voltage; the improvement comprising first logic circuit means in said position detecting circuit having a first binary threshold level below said intermediate level and second logic circuit means in said detecting circuit having a second binary threshold level above said. intermediate level, whereby the occurrence of intermediate level voltages does not alter the monotonic operation of said digital to analog converter.

Claim 2

Dependent Claim 225 words

A parallel comparison analog to digital converter of the type having; a voltage dividing circuit for generating a plurality of ordered comparison voltages; an equal plurality of ordered comparison circuits for comparing said plurality of voltages, respectively, with a common analog input voltage to be digitally converted; a position detecting circuit responsive to the outputs of said plurality of comparison circuits for developing a digital output dependent upon the order of the crossover between those comparison circuits which receive a lower comparison voltage than said common analog input voltage and those comparison circuits which receive a higher comparison voltage than said common analog input voltage; said comparison circuits being of the type which' produce a first binary level output when said analog input voltage is sufficiently above said comparison voltage, a second binary level output when said analog input voltage is sufficiently below said comparison voltage, and an intermediate level output when said analog input is neither sufficiently above nor sufficiently below said comparison voltage; the improvement comprising first logic circuit means in said position detecting circuit having a first binary threshold level below said intermediate level and second logic circuit means in said detecting circuit having a second binary threshold level above said. intermediate level, whereby the occurrence of intermediate level voltages does not alter the monotonic operation of said digital to analog converter.

Claim 3

Dependent Claim 72 words

A parallel comparison analog to digital converter as claimed in claim 1, wherein said first logic circuit means comprises; an ordered plurality of AND gates; each AND gate receiving as a first input the output from the comparison circuit of the same order, the input terminals of each said AND gate having a threshold level at which the gate distinguishes between a "0" and a "1'' at said first binary threshold level.

Claim 4

Dependent Claim 106 words

A parallel comparison analog to digital converter as claimed in claim 2, wherein said second logic circuit means comprises; an ordered plurality of invert gates; each invert gate having its output connected to a second input of the AND gate of the same order; each invert gate, except for the first in the order of invert gates, having its input connected to the output of the comparison circuit which precedes it by one in the order; the input terminal of each said invert gate having a threshold level of which the invert gate distinguishes between a "0" and a "1" at said second binary threshold level.

Claim 5

Dependent Claim 26 words

A parallel comparison analog to digital converter as claimed in claim 3, wherein said first binary threshold level is lower than said second binary threshold level.

Claim 6

Dependent Claim 46 words

A parallel comparison analog to digital converter as claimed in claim 4, wherein the output of each comparison circuit, except for the first comparison circuit in the order, is applied to a third input of the AND gate which precedes it by one in the order.

Claim 7

Dependent Claim 70 words

A parallel comparison analog to digital converter as claimed in claim 1, wherein said first logic circuit means comprises; an ordered plurality of invert gates; each invert gate having as its input the output from the comparison circuit of the same order; the input terminal of each said invert gate having a threshold level at which the gate distinguishes between a="0" and a "1" at said first binary threshold level.

Claim 8

Dependent Claim 108 words

A parallel comparison analog to digital converter as claimed in claim 6, wherein said second logic circuit means comprises; an ordered plurality of NOR gates; each said NOR gate having a first input connected to the output of the invert gate of the same order; each said NOR gate, except for the first of said order, having a second input connected to the output of the comparison circuit which precedes it by one in the order; the input terminals of each said NOR gate having a threshold level at which the gate dis- tin g uishes between a "0" and a "1" at said second binary threshold level.

Claim 9

Dependent Claim 26 words

A parallel comparison analog to digital converter as claimed in claim 7, wherein said first binary threshold level is lower than said second binary threshold level.

Claim 10

Dependent Claim 43 words

A parallel comparison analog to digital converter as claimed in claim 8, wherein each invert gate, except for the first in the order, has its output connected to a third input of the NOR gate which precedes it by one in the order.

Claim 11

Dependent Claim 143 words

A parallel comparison type analog to digital converter, comprising; a voltage dividing circuit for generating an ordered plurality of comparison voltages; an ordered plurality of comparators, each comparing an analog signal with the comparison voltages of the same order as the comparator; a position _.detecting circuit coupled to said comparators for digitizing a value of said analog signal; said position =detecting circuit including a plurality of logic gates each having a first logic input terminal receiving an output signal from the comparator of the same order and a second logic input terminal receiving an output signal from the comparator which precede the gate by one in the order, threshold values of said first and second logic input terminals being made different from each other, and a decoder circuit for generating a digital output in response to the output of said position detecting circuit.

Claim 12

Dependent Claim 143 words

A parallel comparison type analog to digital converter, comprising; a voltage dividing circuit for generating an ordered plurality of comparison voltages; an ordered plurality of comparators, each comparing an analog signal with the comparison voltages of the same order as the comparator; a position _.detecting circuit coupled to said comparators for digitizing a value of said analog signal; said position =detecting circuit including a plurality of logic gates each having a first logic input terminal receiving an output signal from the comparator of the same order and a second logic input terminal receiving an output signal from the comparator which precede the gate by one in the order, threshold values of said first and second logic input terminals being made different from each other, and a decoder circuit for generating a digital output in response to the output of said position detecting circuit.

Claim 13

Dependent Claim 71 words

The converter according to claim 10, in which each of said logic gates includes an AND gate having a first input terminal and a second input terminal and an inverter having an output coupled to the second input terminal of said AND gate, said first input terminal of said AND gate serving as said first logic input terminal and the input of said inverter serving as said second logic input terminal.

Claim 14

Dependent Claim 75 words

The converter according to claim 10, in which each of said logic gates includes a NOR circuit having first and second input terminals, and an inverter having an output coupled to said first input terminal of said NOR circuit, said second input terminal of said NOR circuit serving as said second logic input terminal of said logic gate, the input terminal of said inverter serving as said first logic input terminal of said logic gate.

Claim 15

Dependent Claim 24 words

The converter according to claim 10, in which said voltage dividing circuit includes a plurality of resistors connected in series between two different voltages.

Claim 16

Dependent Claim 48 words

The converter according to claim 10, in which said decoder circuit includes a read only memory circuit storing Gray code data and a conversion circuit coupled to said read only memory circuit for converting the output of said read only memory circuit to a regular binary coded signal.

Claim 17

Dependent Claim 194 words

A parallel comparison type analog to digital converter comprising; means for receiving an analog signal; a voltage generation circuit for generating a plurality of comparison voltages of different values; a plurality of comparator circuits, each having a first input terminal receiving said analog signal and a second input terminal receiving an associated one of said comparison voltages; each of said comparator circuits being weighted by the comparison voltage applied thereto, a plurality of logic gates each having a first logic input terminal receiving an output signal from an associated one of said comparator circuits and a second logic input terminal receiving an output signal from the comparator circuit having the subsequent weight to said associated one of said comparator circuit, each of said logic gates generating an active level output when said first input logic input' terminal thereof is at a first logic level and said second logic input terminal thereof is at a second logic level, threshold values of said first and second logic input terminals of said logic gates being made different from each other, and a decoder circuit coupled to the outputs of said logic gates for generating a digital output.

Claim 18

Dependent Claim 194 words

A parallel comparison type analog to digital converter comprising; means for receiving an analog signal; a voltage generation circuit for generating a plurality of comparison voltages of different values; a plurality of comparator circuits, each having a first input terminal receiving said analog signal and a second input terminal receiving an associated one of said comparison voltages; each of said comparator circuits being weighted by the comparison voltage applied thereto, a plurality of logic gates each having a first logic input terminal receiving an output signal from an associated one of said comparator circuits and a second logic input terminal receiving an output signal from the comparator circuit having the subsequent weight to said associated one of said comparator circuit, each of said logic gates generating an active level output when said first input logic input' terminal thereof is at a first logic level and said second logic input terminal thereof is at a second logic level, threshold values of said first and second logic input terminals of said logic gates being made different from each other, and a decoder circuit coupled to the outputs of said logic gates for generating a digital output.

Claim 19

Dependent Claim 85 words

The converter according to claim 15, in which each of said logic gates includes an AND circuit having a first input terminal serving as said first logic input terminal of the associated logic gate and a second input terminal, and an inverter circuit having an output terminal coupled to said second input terminal of said AND circuit and an input terminal serving as said second input logic input terminal, the threshold value of said inverter circuit being made higher than that of said AND circuit.

Claim 20

Dependent Claim 89 words

The converter according to claim 15, in which each of said logic gates includes a NOR circuit having a first input terminal and a second input terminal, and an inverter circuit having an output connected to the first input terminal of said NOR circuit; said invert circuit having an input terminal serving as said first logic input terminal; the second input terminal of said NOR circuit serving as said second logic input terminal; a threshold value of said inverter circuit being made lower than that of said NOR circuit.

Claim 21

Dependent Claim 22 words

,18. The converter according to claim 15, in which said decoder circuit includes a read only memory circuit storing a Gray code.

Parallel comparison type analog to digital converter

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