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EP0118182A2
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Pattern processing method
Assignee: PATTERN PROCESSING TECHNOLOGIES Inc
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Filing: 1984-01-25
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Granted: —
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Expires: 2004-01-25
Abstract
Abstract A pattern processing system associates image input patterns with desired response codes. The image input is stored in an image buffer (112) as an addressable array of sample values. An address sequencer (114) provides a sequence of addresses (or "address stream") to the imaged buffer (112) and to a response memory (116). The next address provided by the address sequencer (114) is based upon the current address and the state of the sample value stored in the image buffer (112) at the location corresponding to the current address. Once the address sequencer (114) repeats an address, the address stream is in a repetitive address loop as long as the image stored in the image buffer (112) remains constant. The address loop continues to be generated, since the address sequencer (114) always produces the same next address based upon the same current address and the same sample value stored at that current address. During a training mode, a pattern to be recognized is supplied to the image buffer (112) and a training code representing a desired response is written into the response memory (116) at selected locations that correspond to addresses in the address loop being generated. During a later recognition mode, when the same pattern is supplied to the image buffer (112), the same address loop is again generated. The previously stored training codes are read from the response memory (116). A response detector (120) provides a response code output representative of the pattern based upon the most frequent code read out from the response memory (116).
Inventors
- 👤 Larry J. Werth
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 12:02
CPC Classifications
G; G08; G08B; G08B13/00; G08B13/18; G08B13/189; G08B13/194; G06; G06T; G06T7/00; G06V; G06V10/00; G06V10/70; G06V10/74; G06V10/75
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
123 words
A pattern processing system comprising: addressable means for providing sample values representative of an image input pattern at a plurality of addressable locations; address sequencer means for providing an address stream containing a sequence of addresses in which each next address of the sequence is determined by a preceding address and the sample value from the location corresponding to the preceding address; so that upon repetition of an address which has previously been provided in the sequence, the address stream cycles repetitively through an address loop which is a function of the image input pattern; and means responsive to the address stream for identifying image input patterns based upon the address loops which they cause to be provided by the address sequencer means.
Claim 2
Dependent Claim
123 words
A pattern processing system comprising: addressable means for providing sample values representative of an image input pattern at a plurality of addressable locations; address sequencer means for providing an address stream containing a sequence of addresses in which each next address of the sequence is determined by a preceding address and the sample value from the location corresponding to the preceding address; so that upon repetition of an address which has previously been provided in the sequence, the address stream cycles repetitively through an address loop which is a function of the image input pattern; and means responsive to the address stream for identifying image input patterns based upon the address loops which they cause to be provided by the address sequencer means.
Claim 3
Dependent Claim
110 words
The pattern processing system of claim 1 wherein the means responsive to the address stream comprises: response memory means for storing codes in a second array of locations addressable by the address stream; training controller means for selectively causing a predetermined training code to be associated with a selected image input pattern to be written into the response memory means at locations of the second array addressed by the address stream when the selected image input pattern is addressed by the address sequencer means; and response detector means for providing an an output response based upon codes read out from locations of the second array addressed by the address stream.
Claim 4
Dependent Claim
63 words
The pattern processing system of claim 1 wherein each next address of the sequence provided by the address sequencer means has a plurality of possible values based upon the preceding address, and wherein the sample value from the location corresponding to the preceding address determines which of the plurality of possible values is provided by the address sequencer means as the next address.
Claim 5
Dependent Claim
119 words
The pattern processing system of claim 3 wherein the address sequencer means comprises: a plurality of address sequencers, each address sequencer providing a sequence of addresses in which the next address of the sequence has a plurality of possible values depending on a preceding address provided by the address sequencer, and in which the sample value from the preceding address provided by the address sequencer determines which of the plurality of possible values is provided as the next address, so that each address sequencer of the plurality generates an address loop which is a function of the image input pattern; and means for interleaving the sequence of addresses from the plurality of address sequences to produce the address stream.
Claim 6
Dependent Claim
139 words
A pattern processing system for identifying a pattern, the system comprising: means for generating an address stream containing at least one sequence of addresses in which each next address of the sequence has a plurality of possible next address values based upon at least one preceding address, and wherein the next address is selected.. from among the possible next address values based upon at least one sample value related to the one preceding address so that at least one repetitive address loop which is a function of the pattern is generated; means for providing sample values representative of sampled elements of a pattern as a function of addresses of the address stream; and means for identifying the pattern based upon the sequence of addresses generated when the pattern is sampled as a function of addresses of the address stream.
Claim 7
Dependent Claim
139 words
A pattern processing system for identifying a pattern, the system comprising: means for generating an address stream containing at least one sequence of addresses in which each next address of the sequence has a plurality of possible next address values based upon at least one preceding address, and wherein the next address is selected.. from among the possible next address values based upon at least one sample value related to the one preceding address so that at least one repetitive address loop which is a function of the pattern is generated; means for providing sample values representative of sampled elements of a pattern as a function of addresses of the address stream; and means for identifying the pattern based upon the sequence of addresses generated when the pattern is sampled as a function of addresses of the address stream.
Claim 8
Dependent Claim
93 words
The pattern processing system of claim 5 wherein the means for identifying the pattern comprises: response memory means for storing codes in locations addressable by the address stream; training controller means for selectively causing a predetermined training code associated with the pattern to be written into the response memory means at locations addressed by the address stream when the pattern is addressed by the address sequencer means; and response detector means for providing an output response based upon codes read out from locations of the response memory means addressed by the address stream.
Claim 9
Independent Claim
117 words
A method of associating an input pattern with an output response, wherein the input pattern comprises a plurality of sample values, the method comprising: storing the sample values of the input pattern in a first array of addressable locations; sequentially addressing the first array with a sequence of addresses in which each next address of the sequence is determined by a preceding address of the sequence and the sample value stored at the addressable location of the first array corresponding to the preceding address, so that a repetitive address loop which is a function of the input pattern is generated; and associating the output response with the address loop which is a function of the input pattern.
Claim 10
Independent Claim
117 words
A method of associating an input pattern with an output response, wherein the input pattern comprises a plurality of sample values, the method comprising: storing the sample values of the input pattern in a first array of addressable locations; sequentially addressing the first array with a sequence of addresses in which each next address of the sequence is determined by a preceding address of the sequence and the sample value stored at the addressable location of the first array corresponding to the preceding address, so that a repetitive address loop which is a function of the input pattern is generated; and associating the output response with the address loop which is a function of the input pattern.
Claim 11
Dependent Claim
80 words
The method of claim 7 wherein associating the output response with the address loop comprises: sequentially addressing a second array of addressable locations with the sequence of addresses; storing a code representative of the output response at selected locations of the second array which are addressed by the sequence of addresses; reading codes from the locations of the second array addressed by the sequence of addresses; and providing the output response based upon the codes read from the second array.
Claim 12
Independent Claim
96 words
A method of associating a pattern with an output response, the method comprising: sequentially sampling elements of the pattern to produce sample values representative of the sample elements, the elements sampled being selected by a sequence of addresses in which each next address of the sequence is determined by a preceding address of the sequence and the sample value corresponding to the preceding address, so that a repetitive address loop which is a function of the pattern is generated; and associating the output response with the address loop which is a function of the input pattern.
Claim 13
Independent Claim
96 words
A method of associating a pattern with an output response, the method comprising: sequentially sampling elements of the pattern to produce sample values representative of the sample elements, the elements sampled being selected by a sequence of addresses in which each next address of the sequence is determined by a preceding address of the sequence and the sample value corresponding to the preceding address, so that a repetitive address loop which is a function of the pattern is generated; and associating the output response with the address loop which is a function of the input pattern.
Claim 14
Dependent Claim
74 words
The method of claim 9 wherein associating the output response with the address loop comprises: sequentially addressing a response memory with the sequence of addresses; storing a code representative of the output response at selected locations of the response memory which are addressed by the sequence; reading codes from locations of the response memory which are addressed by the sequence; and providing the output response based upon the codes read from the response memory.
Claim 15
Dependent Claim
210 words
A pattern processing system for associating an input pattern comprising a plurality of sample values with an output response, the system comprising: image buffer means for storing the sample values of the input pattern in a first array of addressable locations; response memory means for storing codes in a second array of addressable locations; address sequencer means for providing a sequence of addresses, a next address of the sequence being determined by a preceding address and the sample value stored by the image buffer means at the location corresponding to the preceding address; so that upon repetition of an address which has been previously provided, the sequence of addresses cycles repetitively through an address loop which is a function of the input pattern; training controller means for selectively causing a predetermined code associated with the input pattern to be written into the response memory means at locations of the second array determined by the addresses of an address loop produced when the input pattern is stored by the image buffer means and addressed by the address sequencer means; and response detector means for providing the output response based upon codes read out from locations of the second array addressed by the sequence of addresses provided by the address sequencer means.
Claim 16
Dependent Claim
210 words
A pattern processing system for associating an input pattern comprising a plurality of sample values with an output response, the system comprising: image buffer means for storing the sample values of the input pattern in a first array of addressable locations; response memory means for storing codes in a second array of addressable locations; address sequencer means for providing a sequence of addresses, a next address of the sequence being determined by a preceding address and the sample value stored by the image buffer means at the location corresponding to the preceding address; so that upon repetition of an address which has been previously provided, the sequence of addresses cycles repetitively through an address loop which is a function of the input pattern; training controller means for selectively causing a predetermined code associated with the input pattern to be written into the response memory means at locations of the second array determined by the addresses of an address loop produced when the input pattern is stored by the image buffer means and addressed by the address sequencer means; and response detector means for providing the output response based upon codes read out from locations of the second array addressed by the sequence of addresses provided by the address sequencer means.
Claim 17
Dependent Claim
275 words
A pattern processing system for associating an input pattern comprising a plurality of sample values with an output response during a training mode and subsequently providing the output response when the selected input pattern is present during a subsequent identifying mode, the system comprising: means for storing the storing sample values of the input pattern in a first array of addressable locations; means for storing codes in a second array of addressable locations; means for providing a sequence of addresses corresponding to addressable locations of the first and second arrays, a next address of the sequence being determined by a preceding address of the sequence and the sample value stored at the location at the first array corresponding to the preceding address; so that upon repetition of an address which has been previously provided, the sequence of addresses cycles repetitively through an address loop which is a function of the input pattern and which includes a plurality of addresses, as long as the input pattern remains unchanged; means for causing a predetermined code representative of the output response to be stored at selected locations of the second array determined by the addresses of the address loop produced during the training mode when the sample values of the input pattern are stored in the first array and are addressed by the sequence of addresses; and means for providing the output response based upon the codes read out from locations of the second array addressed by the sequence of addresses generated during the identifying mode when the sample values of the input pattern are stored in the first array and are addressed by the sequence of addresses.
Claim 18
Dependent Claim
275 words
A pattern processing system for associating an input pattern comprising a plurality of sample values with an output response during a training mode and subsequently providing the output response when the selected input pattern is present during a subsequent identifying mode, the system comprising: means for storing the storing sample values of the input pattern in a first array of addressable locations; means for storing codes in a second array of addressable locations; means for providing a sequence of addresses corresponding to addressable locations of the first and second arrays, a next address of the sequence being determined by a preceding address of the sequence and the sample value stored at the location at the first array corresponding to the preceding address; so that upon repetition of an address which has been previously provided, the sequence of addresses cycles repetitively through an address loop which is a function of the input pattern and which includes a plurality of addresses, as long as the input pattern remains unchanged; means for causing a predetermined code representative of the output response to be stored at selected locations of the second array determined by the addresses of the address loop produced during the training mode when the sample values of the input pattern are stored in the first array and are addressed by the sequence of addresses; and means for providing the output response based upon the codes read out from locations of the second array addressed by the sequence of addresses generated during the identifying mode when the sample values of the input pattern are stored in the first array and are addressed by the sequence of addresses.
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