Patent EP0117903A2 successfully refreshed from Google Patents.
EP0117903A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory device with decoding arrangement
Assignee: NEC Corp
•
Filing: 1983-11-15
•
Granted: —
•
Expires: 2003-11-15
Abstract
Abstract A semiconductor memory device which is hardly affected by short-circuiting between word lines and can be fabricated with a high integration density is disclosed. The memory device is featured in that a plurality of word lines are asigned to each decoder in common via plurality of selection circuits and each adjacent word lines are connected to different decoders.
Inventors
- 👤 Hiroshi Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 21:03
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/10; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/4087
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
174 words
A semiconductor memory device comprising a plurality of first word lines, a plurality of second word lines, each of said first word lines and each of said second word lines being alternately arranged in parallel, a plurality of bit lines intersecting with said word lines, a plurality of memory cells arranged at intersections of said word lines and said bit lines, a first decoding circuit, a second decoding circuit, a plurality of control signal terminals, means for operatively supplying one of said control signal terminals with a selection signal, a plurality of first driving transistors each coupled between associated one of said control signal terminals and associated one of said first word lines, first means for controlling said first driving transistors in response to an output of said first decoding circuit, a plurality of second driving transistors each coupled between associated one of said control signal terminals and associated one of said second word lines, and second means for controlling said second driving transistors in response to an output of said second decoding circuit.
Claim 2
Dependent Claim
174 words
A semiconductor memory device comprising a plurality of first word lines, a plurality of second word lines, each of said first word lines and each of said second word lines being alternately arranged in parallel, a plurality of bit lines intersecting with said word lines, a plurality of memory cells arranged at intersections of said word lines and said bit lines, a first decoding circuit, a second decoding circuit, a plurality of control signal terminals, means for operatively supplying one of said control signal terminals with a selection signal, a plurality of first driving transistors each coupled between associated one of said control signal terminals and associated one of said first word lines, first means for controlling said first driving transistors in response to an output of said first decoding circuit, a plurality of second driving transistors each coupled between associated one of said control signal terminals and associated one of said second word lines, and second means for controlling said second driving transistors in response to an output of said second decoding circuit.
Claim 3
Dependent Claim
73 words
The memory device according to claim 1, in which said first means includes a plurality of first transfer gate transistors each coupled between the output of said first decoding circuit and a gate of associated one of said first driving transistors, and said second means includes a plurality of second transfer transistors each couple between the output of said second decoding circuit and a gate of associated one of said second driving transistors.
Claim 4
Dependent Claim
40 words
The memory device according to claim 1, in which one of said first driving transistors and one of said second transistors both connected to the adjacent first and second word lines are commonly connected to the same control signal terminal.
Claim 5
Dependent Claim
24 words
The memory device according to claim 1, in which each of said first and second decoding circuits includes a NOR circuit receiving address signals.
Claim 6
Dependent Claim
149 words
A semiconductor memory device comprising a plurality of memory arrays, each of said memory arrays including a plurality of decoding circuits, a plurality word lines, a plurality of selection lines, a plurality sets of driving transistors, each set of said transistors being controlled by associated one of said decoding circuits and asigned to a part of said word lines which are arrayed at leaped locations from each other, each of said driving transistors in each set of said driving transistors being coupled between one of said selection lines and one of said part of word lines at the leaped locations, a plurality of bit lines intersecting with said word lines, a plurality of memory cells arranged at intersections of said word lines and said bit lines, and-a plurality of control means each controlling associated set of said driving transistors in response to an output of the associated decoding circuit.
Claim 7
Dependent Claim
149 words
A semiconductor memory device comprising a plurality of memory arrays, each of said memory arrays including a plurality of decoding circuits, a plurality word lines, a plurality of selection lines, a plurality sets of driving transistors, each set of said transistors being controlled by associated one of said decoding circuits and asigned to a part of said word lines which are arrayed at leaped locations from each other, each of said driving transistors in each set of said driving transistors being coupled between one of said selection lines and one of said part of word lines at the leaped locations, a plurality of bit lines intersecting with said word lines, a plurality of memory cells arranged at intersections of said word lines and said bit lines, and-a plurality of control means each controlling associated set of said driving transistors in response to an output of the associated decoding circuit.
Claim 8
Dependent Claim
20 words
The memory device according to claim 5, in which said selection lines are common to said plurality of memory arrays.
Claim 9
Dependent Claim
37 words
The memory device according to claim 5, in which each of said control means includes a plurality of transfer gate transistors coupled between the output of the associated decoding circuit and the associated set of driving transistors.
Claim 10
Dependent Claim
17 words
The memory device according to claim 5, in which said plurality of memory arrays operate in parallel.
Claim 11
Dependent Claim
106 words
A semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, a plurality of memory cells, a plurality of selection terminals, a plurality of decoding circuits, a plurality sets of driving transistors, each set of said driving transistors being controlled by the output of associated one of said decoding circuits and assigned to a part of word lines which are not adjacent each other, each transistor of said each set of driving transistor coupled between one of said selection terminals and one of said part of word lines, and means for operalitively supplying one of said selection terminals with a selection signal.
Claim 12
Dependent Claim
106 words
A semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, a plurality of memory cells, a plurality of selection terminals, a plurality of decoding circuits, a plurality sets of driving transistors, each set of said driving transistors being controlled by the output of associated one of said decoding circuits and assigned to a part of word lines which are not adjacent each other, each transistor of said each set of driving transistor coupled between one of said selection terminals and one of said part of word lines, and means for operalitively supplying one of said selection terminals with a selection signal.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.