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EP0117683A2
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Incremental encoder synchronous decode circuit
Assignee: Texas Instruments Inc
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Filing: 1984-02-15
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Granted: —
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Expires: 2004-02-15
Abstract
Abstract A synchronous decode circuit 10 for an incremental encoder is disclosed which comprises analog-to-digital converters 16 for converting in phase and quadrature encoder signals to transistor-to-transistor logic (TTL) compatible signals, a latch 24 for receiving current logic level signals and the previous logic level signals for a gray code, a programmable read only memory (PROM) 32 for decoding the logic level signals and generating clock and direction enable signals, and gating logic 38 connected to the PROM for gating clock and direction signals to counters 52 of the system, the counters 52 are connected to a latch 56 under control of the computer to latch the count of movement in preselected directions for the computer. In another embodiment the PROM includes scaling jumper means or error detection means or both for, respectively, adjusting the range of measurement (scale factor) and indicating error in the logic level signals.
Inventors
- 👤 Martin A. Wand
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 12:45
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/22; H03M1/24; H03M1/28; H03M1/30
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
58 words
A synchronous decode circuit comprising an encoder decode means 10 for receiving incremental movement signals and direction of movement indicating signals, said encoder decode means including a synchronizing means 24 for synchronizing successive pairs of incremental signals and direction movement signals, and clock generating means 32 and 38 operatively connected to the synchronizing means for generating motion information.
Claim 2
Dependent Claim
58 words
A synchronous decode circuit comprising an encoder decode means 10 for receiving incremental movement signals and direction of movement indicating signals, said encoder decode means including a synchronizing means 24 for synchronizing successive pairs of incremental signals and direction movement signals, and clock generating means 32 and 38 operatively connected to the synchronizing means for generating motion information.
Claim 3
Dependent Claim
16 words
A synchronous decode circuit according to Claim 1 wherein the synchronizing means is a latch circuit.
Claim 4
Dependent Claim
59 words
A synchronous decode circuit according to Claim 1 wherein the clock generating means comprises a clock enable and direction enable signal producing means operatively connected to synchronizing means for producing clock enable and direction enable signals, and gating logic means operatively connected to the clock enable and direction enable signal producing means for producing timing information and direction information.
Claim 5
Dependent Claim
25 words
The synchronous decode circuit according to Claim 3 wherein said clock enable and direction enable signal producing means is a decode programmable read only memory.
Claim 6
Dependent Claim
34 words
A synchronous decode circuit according to Claim 4 wherein the decode programmable read only memory further includes scale factor means for adjusting the measurement scale amongst 1, 2, and 4 counter clocks per cycle.
Claim 7
Dependent Claim
70 words
A synchronous decode circuit according to Claim 4 wherein- the decode programmable read only memory further includes a code error detector means, said code error detector means having a latch operatively connected to the decode programmable read only memory for feeding back an error indicating signal to an input of the decode programmable read only memory for the next output thereby providing a debouncing latching action for accurate error detection.
Claim 8
Dependent Claim
37 words
A synchronous decode circuit according to Claim 1 further including an analog-to-digital converter means for receiving analog in phase and quadrature signals representing, respectively, movement and direction of movement and converting the analog signals to digital signals.
Claim 9
Dependent Claim
154 words
A synchronous decode circuit for decoding the output of a servo driven incremental encoder comprising: a) an analog-to-digital converter means said means including connector means for connecting in phase signals and quadrature signals of the incremental encoder and a plurality of analog-to-digital conversion means operatively connected to the connector means for digitizing the analog in phase and quadrature signals; b) a synchronizing means operatively connected to the analog-to-digital conversion means for forming pairs of coded signals from the digitized in phase and quadrature signals and pairing a current pair with a preceding pair for output; c) a comparator means for sequentially comparing the coded pair with a reference pair for determining selectively movement and direction of movement; and d) gating means operatively connected to the comparator means for selectively outputting periodically signals representative of movement and direction of movement whereby a counting of the movement signals and the direction of movement can be made.
Claim 10
Dependent Claim
154 words
A synchronous decode circuit for decoding the output of a servo driven incremental encoder comprising: a) an analog-to-digital converter means said means including connector means for connecting in phase signals and quadrature signals of the incremental encoder and a plurality of analog-to-digital conversion means operatively connected to the connector means for digitizing the analog in phase and quadrature signals; b) a synchronizing means operatively connected to the analog-to-digital conversion means for forming pairs of coded signals from the digitized in phase and quadrature signals and pairing a current pair with a preceding pair for output; c) a comparator means for sequentially comparing the coded pair with a reference pair for determining selectively movement and direction of movement; and d) gating means operatively connected to the comparator means for selectively outputting periodically signals representative of movement and direction of movement whereby a counting of the movement signals and the direction of movement can be made.
Claim 11
Dependent Claim
83 words
A synchronous decode circuit according to Claim 8 wherein said comparator means further includes a code error detector means comprising a decode programmable read only memory including a signal generating means for generating an error signal when a pair of coded in phase and quadrature signals are not included in the reference code of the read only memory and a latch operatively connected to the decode programmable memory for receiving from and feeding back to the decode programmable memory an error indicating signal.
Claim 12
Dependent Claim
27 words
A synchronous decode circuit according to Claim 9 further including an alarm means operatively connected to the latch for generating an error indicating alarm for an operator.
References Cited (Backward Citations)
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