Word line decoder and driver circuitry

Claim 2

Word line decoder and driver circuitry in which the decoder (T 7 , T 8 ....T n ) selects a group of word lines (WLA, WLB) by changing the logic level of a first node (20) in response to the address of the group, and one of the group of word lines is driven by a respective CMOS inverter (T 1 , T or T 3 , T ) coupled to said first node and selected by one or more of a related set of signals (ø R1 , ø R2 ).

Claim 3

A narrow pitch CMOS word line decoder and driver circuit configuration for a semiconductor memory device comprising: a system clock circuit for generating clock pulses; a system voltage supply; a decoder circuit including at least one p-channel transistor having a source electrode connected to said voltage supply, a gate electrode connected to gating signals and a drain electrode connected to a first node, and a plurality of n-channel address switch transistors, each having a drain electrode connected to said first node, a source electrode connected to ground voltage and a gate electrode connected to a separate one of a plurality of input address signals; an inverter circuit including a pair of transistors, a first one of said pair of transistors having a source electrode connected to said voltage supply, a second one of said pair of transistors having a source electrode connected to ground voltage, said first and second inverter transistors having gate electrodes connected in common to said first node and drain electrodes connected in common to a second node; and means connecting said second node to word lines of said semiconductor memory device.

Claim 4

A narrow pitch CMOS word line decoder and driver circuit configuration for a semiconductor memory device comprising: a system clock circuit for generating clock pulses; a system voltage supply; a decoder circuit including at least one p-channel transistor having a source electrode connected to said voltage supply, a gate electrode connected to gating signals and a drain electrode connected to a first node, and a plurality of n-channel address switch transistors, each having a drain electrode connected to said first node, a source electrode connected to ground voltage and a gate electrode connected to a separate one of a plurality of input address signals; an inverter circuit including a pair of transistors, a first one of said pair of transistors having a source electrode connected to said voltage supply, a second one of said pair of transistors having a source electrode connected to ground voltage, said first and second inverter transistors having gate electrodes connected in common to said first node and drain electrodes connected in common to a second node; and means connecting said second node to word lines of said semiconductor memory device.

Claim 5

A narrow pitch CMOS word line decoder and driver circuit configuration according to Claim 2 wherein said gating signals connected to said at least one p-channnel transistor are clock pulses generated by said system clock circuit.

Claim 6

A narrow pitch CMOS word line decoder and driver circuit configuration according to Claim 2 wherein said gating signals connected to said at least one p-channel transistor are input address signals.

Claim 7

A narrow pitch CMOS word line decoder and driver circuit configuration according to Claim 3 wherein said means connecting said second node to said word lines includes a pair of push-pull transistors having drain electrodes connected in common to each of said word lines, having gate electrodes connected in common to said second node, and a source electrode of one transistor of each of said pair of transistors being connected to row clock pulses from said system clock circuit.

Claim 8

A narrow pitch CMOS word line decoder and driver circuit configuration according to Claim 3 wherein said means connecting said second node to said word lines includes a first pair of push-pull transistors having drain electrodes connected in common to a first word line; gate electrodes connected in common to said second node, the source electrode of one of said first pair of push-pull transistors connected to first row clock pulses from said system clock circuit and the source electrode of said other transistor of said first pair connected to ground voltage; and a second pair of push-pull transistors having drain electrodes connected in common to a second word line, gate electrodes connected in common to said second node, the source electrode of one of said second pair of push-pull transistors connected to second row clock pulses from said system clock circuit and the source electrode of said other transistor of said second pair connected to ground voltage.

Claim 9

A narrow pitch CMOS word line decoder and driver circuit configuration according to Claim 3 wherein said means connecting said second node to said word lines includes a first pair of push-pull transistors having drain electrodes connected in common to a first word line; gate electrodes connected in common to said second node, the source electrode of one of said first pair of push-pull transistors connected to first row clock pulses from said system clock circuit and the source electrode of said other transistor of said first pair connected to said system voltage supply; and a second pair of push-pull transistors having drain electrodes connected in common to a second word line, gate electrodes connected in common to said second node, the source electrode of one of said second pair of push-pull transistors connected to second row clock pulses from said system clock circuit and the source electrode of said other transistor of said second pair connected to said system voltage supply.

Claim 10

A narrow pitch CMOS word line decoder and driver circuit configuration according to Claim 5 further including a clamping transistor connected to each of said word lines and having a gate electrode connected to said system clock circuit and responsive to said clock pulses.

Claim 11

A narrow pitch CMOS word line decoder and driver circuit configuration according to Claim 6 wherein further including a first clamping transistor connected to said first word line including a drain electrode connected to said first word line, a gate electrode connected to said second row clock pulses from said system clock circuit and a source electrode connected to ground voltage; and a second clamping transistor connected to said second word line including a drain electrode connected to said second word line, a gate electrode connected to said first row clock pulses from said system clock circuit and a source electrode connected to ground voltage.

Claim 12

A narrow pitch CMOS word line decoder and driver circuit configuration according to Claim 6 wherein further including a first clamping transistor connected to said first word line including a drain electrode connected to said first word line, a gate electrode connected to said second row clock pulses from said system clock circuit and a source electrode connected to said ground system voltage supply; a second clamping transistor connected to said second word line including a drain electrode connected to said second word line, a gate electrode connected to said first row clock pulses from said system clock circuit and a source electrode connected to said system voltage supply.