EP0116774A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory device with a refresh mechanism
Assignee: Toshiba Corp
•
Filing: 1983-12-20
•
Granted: —
•
Expires: 2003-12-20
Abstract
Abstract A semiconductor memory device with a refresh mechanism having a plurality of memory cells (100) integrated on a semiconductor substrate, a plurality of word lines (W L ) and bit lines (Wd) each connected to the memory cells, a refresh control means (107) for successively selecting the word lines and refreshing the memory cells word line by word line in a refresh period and a timing means (102) connected to the word lines. The timing means (102) is activated whenever the word line connected to it is selected during an access period and emits a 'refresh not required' signal and then causes the next refresh operation to be skipped for that word line.
Inventors
- 👤 Koji C/O Patent Division Sakui
- 👤 Fumio C/O Patent Division Horiguchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 13:44
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
177 words
A semiconductor memory device comprising a plurality of memory cells (100) each consisting of one transistor (1) and one capacitor (2) a plurality of word lines (W L ) for addressing said memory cells, a plurality of digit lines (Wd) for reading and/or writing the data of said memory cells, an access control means (101, 103) for accessing said memory cells by selecting said word lines, a refresh control means (107) for successively selecting said word line connected to each of said memory cells and refreshing said memory cells word line by word line in a refresh period, characterised in that a timing means (102) is connected to each of said word lines, each of said timing means (102) being so arranged that it is activated whenever the word line connected to it is selected during an access period and being arranged to supply a 'refresh not required' signal until a predetermined time has elapsed, said refresh control means (107) being arranged to detect said 'refresh not required' signal and to then select the next word line.
Claim 2
Dependent Claim
177 words
A semiconductor memory device comprising a plurality of memory cells (100) each consisting of one transistor (1) and one capacitor (2) a plurality of word lines (W L ) for addressing said memory cells, a plurality of digit lines (Wd) for reading and/or writing the data of said memory cells, an access control means (101, 103) for accessing said memory cells by selecting said word lines, a refresh control means (107) for successively selecting said word line connected to each of said memory cells and refreshing said memory cells word line by word line in a refresh period, characterised in that a timing means (102) is connected to each of said word lines, each of said timing means (102) being so arranged that it is activated whenever the word line connected to it is selected during an access period and being arranged to supply a 'refresh not required' signal until a predetermined time has elapsed, said refresh control means (107) being arranged to detect said 'refresh not required' signal and to then select the next word line.
Claim 3
Dependent Claim
113 words
A semiconductor memory device according to claim 1, wherein said refresh control means (107) includes; a pulse generator (11), a row address counter (10) for successively selecting said word lines in accordance with pulse signals from said pulse generator, a first circuit means (12) for detecting the data in said row address counter and emitting a pulse signal indicating the end of said refresh period, and a second circuit means (15) for incrementing said row address counter by 1 when said 'refresh not required' signal is supplied from said timing means and stopping an incrementation of said row address counter when said 'refresh not required' signal is not supplied from said timing means.
Claim 4
Dependent Claim
66 words
A semiconductor memory device according to claim 1 or claim 2, wherein said timing means (102) includes; a capacitor (32) arranged to be charged on selection of said word line, a resistor (31) connected in parallel to said capacitor so as to discharge said capacitor with a time constant CR, where R is the resistance of said resistor and C is the capacitance of said capacitor.
Claim 5
Dependent Claim
15 words
A semiconductor memory device according to claim 3, wherein said time constant CR is variable.
Claim 6
Dependent Claim
34 words
A semiconductor memory device according to any preceding claim, wherein said transistor (1) is a MOS transistor whose gate is connected to said word line and whose drain is connected to said digit line.
Claim 7
Dependent Claim
30 words
A semiconductor memory device according to any preceding claim, wherein said capacitor (2) is a MOS capacitor which stores the data for storage in the form of an electric charge.
Claim 8
Dependent Claim
20 words
A semiconductor memory device according to any preceding claim, wherein said plurality of memory cells comprise a random access memory.
Claim 9
Dependent Claim
112 words
A semiconductor memory device according to any preceding claim in which said memory cells (100) are divided into a plurality of blocks (A-E), the first word lines (WL A -WL E ) of each of the blocks being connected to respective timing means (102) which are activated whenever said first word line connected to it is selected during an access period and emitting a 'refresh not required' signal until a predetermined time has elapsed, whereby said refresh control means (107) selects in said refresh period all of the word lines in the first block whose word line is connected to a timing means which does not emit said 'refresh not required' signal.
Claim 10
Dependent Claim
47 words
A semiconductor memory device according to claim 8, wherein said refresh control means (107) includes a circuit (10, 51, 54) for supplying row address signals corresponding to the first word line of each of said blocks when said time constant means emits said 'refresh not required' signal.
References Cited (Backward Citations)
US3737879A
Cited
US4292676A
Cited
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.