Patent EP0113828A2 successfully refreshed from Google Patents.
EP0113828A2
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EP
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Master slice semiconductor chip having a new multi-function FET cell
Assignee: International Business Machines Corp
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Filing: 1983-11-10
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Granted: —
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Expires: 2003-11-10
Abstract
Abstract A cell layout provides a practical masterslice design for random logic in any LSI FET technology. Each cell is capable of the order of about 20 different functions at any of several different power levels. Multiple cells can be combined to form standard macro functions.
Inventors
- 👤 Joseph Michael Fitzgerald
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 03:06
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/08; H03K19/094; H03K19/0944; H03K19/09441; H03K19/09443; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
18 words
A multifunction FET masterslice cell (12) occupying a shape within a boundary characterized in that it comprises :
Claim 2
Dependent Claim
181 words
A masterslice semiconductor chip (10) carrying an array of repetitive multifunction cells (12) each occupying a shape within a boundary and characterized in that each cell is comprised of : (a) A group of parallel semiconductive columns (312); (b) a first insulating layer overlying said columns; (c) A group of parallel conductive rows (345-350) overlying said first insulating layer perpendicular to said columns, so as to form a grid of interconnected logic FET devices (TF-TO) having gate electrodes defined by said rows and source and drain electrodes defined by said columns; (d) a first group of vias (V1-V21) extending upwardly through said first insulating layer within said cell for connecting said source and drain electrodes to a personalizable interconnection layer above said rows; (e) a group of I/O pads (V21-V25) disposed near said boundary and connected to at least some of said rows for connecting said rows to a personalizable interconnection level above said rows; (f) load means including a group of load FET devices (TA-TE) selectively connectable to said logic FET devices and to a supply voltage (V dd ).
Claim 3
Dependent Claim
25 words
A chip according to claim 1, wherein at least some of said cells are disposed in a group of parallel lines (13) on said chip.
Claim 4
Dependent Claim
22 words
A chip according to claim 2, wherein at least some of said lines are separated by a group of wiring bays (14).
Claim 5
Dependent Claim
24 words
A chip according to claim 3, wherein said cell boundary is a rectangle having at least one edge adjacent one of said wiring bays.
Claim 6
Dependent Claim
16 words
A chip according to claim 4, wherein said I/O pads are disposed along said one edge.
Claim 7
Dependent Claim
26 words
A chip according to claim 2, wherein at least some of said lines are disposed in pairs each separated from the next by a wiring bay.
Claim 8
Dependent Claim
30 words
A chip according to claim 6, wherein at least some of the adjacent cells (12, 12') in said pairs of lines are symmetric about an axis parallel to said lines.
Claim 9
Dependent Claim
26 words
A chip according to claim 2, wherein at least some of the adjacent cells in said lines are symmetric about an axis perpendicular to said lines.
Claim 10
Dependent Claim
34 words
A chip according to claim 1, wherein said load means includes a first group of load FET devices having drain electrodes connected to each other and to a via communicating with said supply voltage.
Claim 11
Dependent Claim
30 words
A chip according to claim 9, wherein said first group of load devices have sources individually connected to vias through said first insulating layer communicating with a personalizable interconnection level.
Claim 12
Dependent Claim
33 words
A chip according to claim 10, wherein at least some of said first group of load devices have gates connected to each other and to a via communicating with a personalizable interconnection level.
Claim 13
Dependent Claim
23 words
A chip according to claim 9, wherein said first group of load devices have source and drain electrodes comprising a single semiconductive shape.
Claim 14
Dependent Claim
34 words
A chip according to claim 9, wherein at least one of said load devices has a source electrode tied directly to a gate electrode and to a via communicating with a personalizable interconnection level.
Claim 15
Dependent Claim
13 words
A chip according to claim 9, wherein said load devices are depletion-FET devices.
Claim 16
Dependent Claim
30 words
A chip according to claim 1, wherein said semiconductive columns each include a continuous diffusion shape such that all said logic FET devices in said column are connected in series.
Claim 17
Dependent Claim
18 words
A chip according to claim 15, wherein said group of semiconductive columns comprises a pair of semiconductive columns.
Claim 18
Dependent Claim
30 words
A chip according to claim 16, wherein said pair of semiconductive columns comprises a single diffusion shape forming said pair of columns and at least one interconnection between said columns.
Claim 19
Dependent Claim
33 words
A chip according to claim 17, wherein said single diffusion shape includes a pair of interconnection shapes between said columns, one of said interconnection shapes being disposed at each end of said columns.
Claim 20
Dependent Claim
25 words
A chip according to claim 15, wherein the vias in said first group alternate with said conductive rows along at least one of said columns.
Claim 21
Dependent Claim
26 words
A chip according to claim 15, wherein at least some of said rows extend continuously across all said columns and to respective ones of said pads.
Claim 22
Independent Claim
237 words
A method for fabricating a personalizable masterslice chip in FET technology on a semiconductor substrate conceptually divided into a pattern of congruent individual cells separated by wiring bays, said method comprising: (a) diffusing into said substrate a group of columns in a first direction in each said cell; (b) diffusing into said substrate at least one load-means shape in each said cell; (c) depositing a first insulating layer on said chip; (d) forming a first group of vias in said insulating layer communicating with said diffusion; (e) forming a second group of vias over said load-means shape; (f) depositing a group of conductive rows in each said cell over said insulating layer and extending across said columns so as to form a grid of series-connected logic FET devices in each said cell; (g) depositing at least one conductive shape over said load-means shape so as to form a group of load FET devices in each said cell; (h) depositing a second insulating layer on said chip; (i) forming a third group of vias in said second insulating layer overlying said first and second groups of vias; (j) forming a fourth group of vias in said second insulating layer communicating with said rows; (k) forming a fifth group of vias in said second insulating layer communicating with said conductive shape over said load-means shape so as to allow connections to individual ones of said group of load devices.
Claim 23
Dependent Claim
15 words
A method according to claim 22, wherein said logic FET devices are N-channel enhancement devices.
Claim 24
Dependent Claim
26 words
A method according to claim 22, further comprising: (1) diffusing an implant into said load-means shape so as to make said load devices N-channel depletion devices.
Claim 25
Dependent Claim
12 words
A method according to claim 24, wherein said conductive rows are polysilicon.
Claim 26
Dependent Claim
49 words
A method according to claim 24, further comprising: (m) depositing a conductive layer on said chip over said second insulating layer so as to form a group of fixed power buses communicating with said columns and said load-means shape through corresponding vias in said first, second, and third groups.
Claim 27
Dependent Claim
40 words
A method according to claim 25, wherein said last-named conductive layer further comprises a group of personalized conductors overlying said cells and communicating with said columns and with said conductive rows through at least some of said groups of vias.
Claim 28
Dependent Claim
33 words
A method according to claim 25, wherein said last-named conductive layer further comprises personalized conductors extending between said cells and communicating with said conductive rows through said fourth and fifth groups of vias.
Claim 29
Dependent Claim
70 words
A method according to claim 27, further comprising: (n) depositing a third insulating layer on said chip over said last-named conductive layer; (o) forming a sixth group of vias in said third insulating layer overlying certain of said last-named conductors; (p) depositing a further conductive layer on said third insulating layer so as to form a further group of personalized conductors extending between certain of said sixth group of vias.
Claim 30
Dependent Claim
51 words
A method according to claim 28, further comprising: (q) forming a seventh group of vias in said third insulating layer overlying certain of said fourth group of vias; (r) forming additional conductors in said further conductive layer communicating with certain of said rows through said fourth and seventh groups of vias.
References Cited (Backward Citations)
No citation records indexed.
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